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More bugfixes related to new RTLIL::IdString

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This commit is contained in:
Clifford Wolf 2014-08-02 16:03:18 +02:00
parent 08392aad8f
commit 768eb846c4
10 changed files with 60 additions and 44 deletions
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14
frontends/ast/simplify.cc
View file

@ -465,10 +465,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
size_t pos = str.rfind('.');
if (pos == std::string::npos)
log_error("Defparam `%s' does not contain a dot (module/parameter seperator) at %s:%d!\n",
RTLIL::id2cstr(str), filename.c_str(), linenum);
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
std::string modname = str.substr(0, pos), paraname = "\\" + str.substr(pos+1);
if (current_scope.count(modname) == 0 || current_scope.at(modname)->type != AST_CELL)
log_error("Can't find cell for defparam `%s . %s` at %s:%d!\n", RTLIL::id2cstr(modname), RTLIL::id2cstr(paraname), filename.c_str(), linenum);
log_error("Can't find cell for defparam `%s . %s` at %s:%d!\n", RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paraname).c_str(), filename.c_str(), linenum);
AstNode *cell = current_scope.at(modname), *paraset = clone();
cell->children.insert(cell->children.begin() + 1, paraset);
paraset->type = AST_PARASET;
@ -1306,7 +1306,7 @@ skip_dynamic_range_lvalue_expansion:;
{
if (children.size() != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
RTLIL::id2cstr(str), int(children.size()), filename.c_str(), linenum);
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
AstNode *buf = children[0]->clone();
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@ -1336,18 +1336,18 @@ skip_dynamic_range_lvalue_expansion:;
if (func_with_two_arguments) {
if (children.size() != 2)
log_error("System function %s got %d arguments, expected 2 at %s:%d.\n",
RTLIL::id2cstr(str), int(children.size()), filename.c_str(), linenum);
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
} else {
if (children.size() != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
RTLIL::id2cstr(str), int(children.size()), filename.c_str(), linenum);
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
}
if (children.size() >= 1) {
while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (!children[0]->isConst())
log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n",
RTLIL::id2cstr(str), filename.c_str(), linenum);
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
int child_width_hint = width_hint;
bool child_sign_hint = sign_hint;
children[0]->detectSignWidth(child_width_hint, child_sign_hint);
@ -1358,7 +1358,7 @@ skip_dynamic_range_lvalue_expansion:;
while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (!children[1]->isConst())
log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n",
RTLIL::id2cstr(str), filename.c_str(), linenum);
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
int child_width_hint = width_hint;
bool child_sign_hint = sign_hint;
children[1]->detectSignWidth(child_width_hint, child_sign_hint);

18
frontends/liberty/liberty.cc
View file

@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
std::string id = RTLIL::escape_id(std::string(expr, id_len));
if (!module->wires_.count(id))
log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id));
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
expr += id_len;
return module->wires_.at(id);
@ -234,7 +234,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
}
if (clk_sig.size() == 0 || data_sig.size() == 0)
log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::id2cstr(module->name));
log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", log_id(module->name));
for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
{
@ -311,7 +311,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
}
if (enable_sig.size() == 0 || data_sig.size() == 0)
log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::id2cstr(module->name));
log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name));
for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
{
@ -480,10 +480,10 @@ struct LibertyFrontend : public Frontend {
if (design->has(cell_name)) {
if (flag_ignore_redef)
continue;
log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str());
}
// log("Processing cell type %s.\n", RTLIL::id2cstr(cell_name));
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
RTLIL::Module *module = new RTLIL::Module;
module->name = cell_name;
@ -501,9 +501,9 @@ struct LibertyFrontend : public Frontend {
{
if (!flag_ignore_miss_dir)
{
log_error("Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(), RTLIL::id2cstr(module->name));
log_error("Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
} else {
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", RTLIL::id2cstr(module->name), node->args.at(0).c_str());
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
delete module;
goto skip_cell;
}
@ -551,9 +551,9 @@ struct LibertyFrontend : public Frontend {
{
if (!flag_ignore_miss_func)
{
log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name));
log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
} else {
log("Ignoring cell %s with missing function on output %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
delete module;
goto skip_cell;
}