mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Added module->design and cell->module, wire->module pointers

Browse source
This commit is contained in:
Clifford Wolf 2014-07-31 14:11:39 +02:00
parent 1cb25c05b3
commit e6d33513a5
15 changed files with 142 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

10
frontends/ast/ast.cc
View file

@ -936,7 +936,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str = (*it)->str.substr(1);
if (defer)
(*it)->str = "$abstract" + (*it)->str;
if (design->modules_.count((*it)->str)) {
if (design->has((*it)->str)) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@ -944,7 +944,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue;
}
design->modules_[(*it)->str] = process_module(*it, defer);
design->add(process_module(*it, defer));
}
}
@ -1041,10 +1041,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
modname = "$paramod" + stripped_name + para_info;
}
if (design->modules_.count(modname) == 0) {
if (!design->has(modname)) {
new_ast->str = modname;
design->modules_[modname] = process_module(new_ast, false);
design->modules_[modname]->check();
design->add(process_module(new_ast, false));
design->module(modname)->check();
} else {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}

4
frontends/ilang/parser.y
View file

@ -90,12 +90,12 @@ design:
module:
TOK_MODULE TOK_ID EOL {
if (current_design->modules_.count($2) != 0)
if (current_design->has($2))
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
current_module = new RTLIL::Module;
current_module->name = $2;
current_module->attributes = attrbuf;
current_design->modules_[$2] = current_module;
current_design->add(current_module);
attrbuf.clear();
free($2);
} module_body TOK_END {

4
frontends/liberty/liberty.cc
View file

@ -477,7 +477,7 @@ struct LibertyFrontend : public Frontend {
std::string cell_name = RTLIL::escape_id(cell->args.at(0));
if (design->modules_.count(cell_name)) {
if (design->has(cell_name)) {
if (flag_ignore_redef)
continue;
log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
@ -565,7 +565,7 @@ struct LibertyFrontend : public Frontend {
}
module->fixup_ports();
design->modules_[module->name] = module;
design->add(module);
cell_count++;
skip_cell:;
}

4
frontends/verific/verific.cc
View file

@ -482,7 +482,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
{
std::string module_name = nl->IsOperator() ? std::string("$verific$") + nl->Owner()->Name() : RTLIL::escape_id(nl->Owner()->Name());
if (design->modules_.count(module_name)) {
if (design->has(module_name)) {
if (!nl->IsOperator())
log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
return;
@ -490,7 +490,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
RTLIL::Module *module = new RTLIL::Module;
module->name = module_name;
design->modules_[module->name] = module;
design->add(module);
log("Importing module %s.\n", RTLIL::id2cstr(module->name));