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Added module->uniquify()

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This commit is contained in:
Clifford Wolf 2014-08-16 23:50:36 +02:00
parent f82c978e08
commit 7f734ecc09
5 changed files with 29 additions and 15 deletions
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8
frontends/verific/verific.cc
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@ -603,9 +603,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
// log(" importing net %s.\n", net->Name());
std::string wire_name = RTLIL::escape_id(net->Name());
while (module->count_id(wire_name))
wire_name += "_";
RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(net->Name()));
RTLIL::Wire *wire = module->addWire(wire_name);
import_attributes(wire->attributes, net);
@ -627,9 +625,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
{
// log(" importing netbus %s.\n", netbus->Name());
std::string wire_name = RTLIL::escape_id(netbus->Name());
while (module->count_id(wire_name))
wire_name += "_";
RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus);