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Improved scope resolution of local regs in Verilog+AST frontend

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This commit is contained in:
Clifford Wolf 2014-08-05 12:15:53 +02:00
parent 0129d41efa
commit 91dd87e60b
4 changed files with 90 additions and 9 deletions
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2
frontends/ast/ast.h
View file

@ -200,7 +200,7 @@ namespace AST
// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);
void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
void replace_ids(std::map<std::string, std::string> &rules);
void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules);
void mem2reg_as_needed_pass1(std::map<AstNode*, std::set<std::string>> &mem2reg_places,
std::map<AstNode*, uint32_t> &mem2reg_flags, std::map<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);
void mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block);

31
frontends/ast/simplify.cc
View file

@ -794,6 +794,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (children[i]->type == AST_WIRE) {
children[i]->simplify(false, false, false, stage, -1, false, false);
current_ast_mod->children.push_back(children[i]);
current_scope[children[i]->str] = children[i];
} else
new_children.push_back(children[i]);
@ -1492,7 +1493,7 @@ skip_dynamic_range_lvalue_expansion:;
if (child->type != AST_WIRE)
{
AstNode *stmt = child->clone();
stmt->replace_ids(replace_rules);
stmt->replace_ids(prefix, replace_rules);
for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
if (*it != current_block_child)
@ -1855,12 +1856,30 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
}
// rename stuff (used when tasks of functions are instanciated)
void AstNode::replace_ids(std::map<std::string, std::string> &rules)
void AstNode::replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules)
{
if (type == AST_IDENTIFIER && rules.count(str) > 0)
str = rules[str];
for (auto child : children)
child->replace_ids(rules);
if (type == AST_BLOCK)
{
std::map<std::string, std::string> new_rules = rules;
std::string new_prefix = prefix + str;
for (auto child : children)
if (child->type == AST_WIRE) {
new_rules[child->str] = new_prefix + child->str;
child->str = new_prefix + child->str;
}
for (auto child : children)
if (child->type != AST_WIRE)
child->replace_ids(new_prefix, new_rules);
}
else
{
if (type == AST_IDENTIFIER && rules.count(str) > 0)
str = rules.at(str);
for (auto child : children)
child->replace_ids(prefix, rules);
}
}
// helper function for mem2reg_as_needed_pass1

3
frontends/verilog/parser.y
View file

@ -599,12 +599,11 @@ wire_name:
if (node->is_input || node->is_output)
frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
}
ast_stack.back()->children.push_back(node);
} else {
if (node->is_input || node->is_output)
node->port_id = current_function_or_task_port_id++;
current_function_or_task->children.push_back(node);
}
ast_stack.back()->children.push_back(node);
delete $1;
};