1958 commits

Author	SHA1	Message	Date
Martin Povišer	0aab8b4158	Merge pull request #4605 from povik/liberty-unit-delay ... read_liberty: Optionally import unit delay arcs	2024-10-07 16:11:51 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 ... New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	6c1450fdaf	Merge pull request #4607 from povik/ql-nodiv ... quicklogic: Avoid carry chains in division mapping	2024-10-07 16:11:11 +02:00
Martin Povišer	ca5c2fdff1	quicklogic: Relax the LUT number test	2024-10-07 15:27:03 +02:00
Martin Povišer	b01b17689e	Add test of error not getting silenced	2024-10-07 14:49:17 +02:00
Martin Povišer	d0a11e26f3	aiger2: Add test of writing a flattened view	2024-10-07 12:04:33 +02:00
Akash Levy	36e57017fe	Add Liberty to verilog conversion tests	2024-10-05 01:34:12 -10:00
Akash Levy	4de5e718ed	Add two new Liberty test cases	2024-10-05 01:33:56 -10:00
Lofty	13ecbd5c76	quicklogic: test that dividing by a constant does not infer carry chains	2024-10-03 20:05:28 +01:00
Akash Levy	654e92e04e	Fix Liberty issue	2024-10-03 04:14:20 -07:00
Akash Levy	dd487ca8a1	Updating Yosys	2024-10-03 01:46:09 -07:00
Akash Levy	2d8588f15b	Update Verific	2024-10-02 23:09:36 -07:00
Akash Levy	e8d9622a59	wreduce test works now	2024-10-02 17:25:57 -07:00
Roland Coeurjoly	5ea2c6e6e5	Assume x values for missing signal data in FST ... Co-authored-by: Miodrag Milanovic <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-02 12:08:48 +02:00
Emil J. Tywoniak	997cb30f1f	cxxrtl: test stream operator	2024-10-01 13:25:07 +02:00
Roland Coeurjoly	76c615b2ae	Fix: handle VCD variable references with and without whitespace ... Co-authored-by: Miodrag Milanović <mmicko@gmail.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-10-01 11:51:20 +02:00
Akash Levy	ee0b083a1e	Merge branch 'YosysHQ:main' into main	2024-09-30 02:43:09 -07:00
rherveille	ce7db661a8	Added cast to type support (#4284)	2024-09-29 17:03:01 -04:00
George Rennie	0572f8806f	opt_reduce: add test for constant $reduce_and/or not being zero width	2024-09-25 16:28:41 +01:00
George Rennie	e105cae4a9	opt_demorgan: add test for zero width cell	2024-09-25 16:10:16 +01:00
Akash Levy	ed2c65314b	Standardize convention, add back test, update README	2024-09-23 06:06:43 -07:00
Akash Levy	db14842d9c	Skip some various tests and fix scopeinfo to match our convention	2024-09-23 05:39:39 -07:00
Akash Levy	138228d96e	Update Verific README	2024-09-23 05:35:48 -07:00
Akash Levy	fb32031273	Skip combo loop test and mark wreduce as failing (FIXME)	2024-09-23 05:35:27 -07:00
Akash Levy	79a14e2072	Skip opt_lut test	2024-09-23 05:35:03 -07:00
Akash Levy	0fd6e29e8e	Fixups	2024-09-23 04:25:10 -07:00
Akash Levy	2d771a352e	Clean up Verific tests	2024-09-23 04:05:08 -07:00
Akash Levy	2c3d2b3ec6	Clocking works with -formal flag	2024-09-22 08:01:16 -07:00
Akash Levy	69bf7875dd	Small edits	2024-09-22 07:52:58 -07:00
Martin Povišer	ea765686b6	aiger2: Adjust hierarchy/port handling	2024-09-18 16:55:02 +02:00
Martin Povišer	6c1fa45995	aiger2: Ingest $pmux	2024-09-18 16:42:56 +02:00
Martin Povišer	d5756eb9be	tests: Add trivial liberty -unit_delay test	2024-09-18 16:17:03 +02:00
Martin Povišer	31476e89b6	tests: Avoid temporary script file	2024-09-18 16:17:03 +02:00
Martin Povišer	8e29675a23	aiger2: Support $bwmux, comparison operators	2024-09-17 13:55:58 +02:00
Martin Povišer	fb26945a20	Start an 'aiger2' backend	2024-09-17 13:55:58 +02:00
Martin Povišer	4cfdb7ab50	Adjust operation naming in aigmap test	2024-09-17 13:55:58 +02:00
Akash Levy	210ec6585f	Merge branch 'YosysHQ:main' into main	2024-09-16 06:59:25 -07:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00
Akash Levy	285c8a3f66	Merge branch 'YosysHQ:main' into main	2024-09-12 11:14:15 -07:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Emil J. Tywoniak	1e999a3cb7	clockgate: EN can be a bit on a multi-bit wire	2024-09-11 19:18:25 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Emil J. Tywoniak	7e473299bd	clockgate: bail on constant signals	2024-09-09 21:20:19 +02:00
Emil J. Tywoniak	dc039d8be4	clockgate: test fine-grained cells	2024-09-09 21:03:22 +02:00
Emil J. Tywoniak	e64fceef70	clockgate: prototype clock gating	2024-09-09 15:00:54 +02:00
Akash Levy	20c5ed2ebb	Merge latest	2024-09-06 07:43:14 -07:00
Miodrag Milanović	b20df72e1e	Merge pull request #4536 from YosysHQ/functional ... Functional Backend	2024-09-06 10:05:04 +02:00
Emily Schmidt	5a476a8d29	functional tests: run from make tests but not smtlib/rkt tests	2024-09-04 10:30:08 +01:00
Akash Levy	120f69eda7	Merge branch 'YosysHQ:main' into main	2024-09-04 00:02:25 -07:00
Krystine Sherwin	7fe9157df2	smtr: Add rkt to functional tests	2024-09-03 11:32:02 +01:00