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Merge pull request #4607 from povik/ql-nodiv

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quicklogic: Avoid carry chains in division mapping
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Martin Povišer 2024-10-07 16:11:11 +02:00 • committed by GitHub
commit 6c1450fdaf
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3 changed files with 18 additions and 2 deletions
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3
techlibs/common/techmap.v
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@ -304,6 +304,7 @@ endmodule
// Divide and Modulo
// --------------------------------------------------------
`ifndef NODIV
module \$__div_mod_u (A, B, Y, R);
parameter WIDTH = 1;
@ -531,7 +532,7 @@ module _90_modfloor (A, B, Y);
.R(Y)
);
endmodule
`endif
// --------------------------------------------------------
// Power

3
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -266,7 +266,8 @@ struct SynthQuickLogicPass : public ScriptPass {
if (check_label("map_gates")) {
if (inferAdder && family == "qlf_k6n10f") {
run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)");
run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v -D NODIV", "(unless -no_adder)");
run("techmap", "(unless -no_adder)");
} else {
run("techmap");
}

14
tests/arch/quicklogic/qlf_k6n10f/div.ys Normal file
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@ -0,0 +1,14 @@
# division by constants should not infer carry chains.
read_verilog <<EOF
module top (input [15:0] a, output [15:0] y);
assign y = a / 3;
endmodule
EOF
equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-max 100 t:$lut
select -assert-none t:$lut %% t:* %D