mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

opt_reduce: add test for constant $reduce_and/or not being zero width

Browse source
This commit is contained in:
George Rennie 2024-09-25 16:28:41 +01:00
parent 023f029dcf
commit 0572f8806f
1 changed files with 14 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

14
tests/opt/opt_reduce_andor.ys Normal file
View file

@ -0,0 +1,14 @@
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
read_verilog <<EOT
module reduce_const(output wire o, output wire a);
wire [3:0] zero = 4'b0000;
wire [3:0] ones = 4'b1111;
assign o = |zero;
assign a = &ones;
endmodule
EOT
equiv_opt -assert opt_reduce
design -load postopt
select -assert-none r:A_WIDTH=0