Merge branch 'YosysHQ:main' into main

tests/verific/bounds.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity work is
+    Port (
+        a : in INTEGER range -5 to 10;
+        b : out INTEGER range -6 to 11
+    );
+end entity work;
+
+architecture Behavioral of work is
+begin
+    process(a)
+    begin
+        b <= a;
+    end process;
+end architecture Behavioral;

tests/verific/bounds.ys

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+read -vhdl bounds.vhd
+verific -import work
+select -assert-count 1 a:bottom_bound=5'bs11011
+select -assert-count 1 a:top_bound=5'bs01010
+select -assert-count 1 a:bottom_bound=5'bs11010
+select -assert-count 1 a:top_bound=5'bs01011