Add Liberty to verilog conversion tests

tests/liberty_verilog/.gitignore

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+*.log
+test.ys
+*.lib.v

tests/liberty_verilog/bundledef.lib

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+/* Liberty 2007: example 2-4          */
+/* Direction of pins in bundle groups */
+library(bundle_example) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+  cell (inv) {
+    area : 16;
+    cell_leakage_power : 8;
+    bundle (Z) {
+      members (Z0, Z1, Z2, Z3);
+      direction : output;
+      function : "D";
+      pin (Z0) {
+        direction : output;
+        timing () {
+          intrinsic_rise : 0.4;
+          intrinsic_fall : 0.4;
+          related_pin : "D0";
+        }
+      }
+      pin (Z1) {
+        direction : output;
+        timing () {
+          intrinsic_rise : 0.4;
+          intrinsic_fall : 0.4;
+          related_pin : "D1";
+        }
+      }
+    }
+    bundle (D) {
+      members (D0, D1, D2, D3);
+      direction : input;
+      capacitance : 1;
+      pin (D0) {
+        direction : input;
+      }
+    }
+  }
+}

tests/liberty_verilog/bundledef.lib.v.ok

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+(* LeakagePower = "8" *)
+(* area = "16" *)
+(* blackbox =  1  *)
+module inv(Z0, Z1, Z2, Z3, D0, D1, D2, D3);
+  input D0;
+  wire D0;
+  input D1;
+  wire D1;
+  input D2;
+  wire D2;
+  input D3;
+  wire D3;
+  output Z0;
+  wire Z0;
+  output Z1;
+  wire Z1;
+  output Z2;
+  wire Z2;
+  output Z3;
+  wire Z3;
+endmodule

tests/liberty_verilog/busdef.lib

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+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 02-11-2018                      */
+/* Version: 1.0                             */
+/* TODO: FIX THE RESULTS                    */
+/********************************************/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+    type( IO_bus_3_to_0 ) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+    cell (SRAM) {
+        area : 1 ;
+        memory() {
+            type : ram;
+            address_width : 4;
+            word_width : 4;
+        }
+        pin(CE1) {
+            direction : input;
+            capacitance : 0.021;
+            max_transition : 1.024;
+            switch_pin : true;
+        }
+        bus(I1)  {
+            bus_type : IO_bus_3_to_0 ;
+            direction : input;
+            pin (I1[3:0]) {
+                timing() {
+                    related_pin :   "CE1" ;
+                    timing_type : setup_rising ;
+                    rise_constraint (scalar) {
+                        values("0.0507786");
+                    }
+                    fall_constraint (scalar) {
+                        values("0.0507786");
+                    }
+                }
+            }
+        }
+    }
+
+} /* end */

tests/liberty_verilog/busdef.lib.v.ok

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+(* area = "1" *)
+(* blackbox =  1  *)
+module SRAM(CE1, I1);
+  input CE1;
+  wire CE1;
+  input [3:0] I1;
+  wire [3:0] I1;
+endmodule

tests/liberty_verilog/busdef2.lib

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+/* Tests two things:                                                      */
+/* (1) Bus without any individual pin definition                          */
+/* (2) Having a custom field with define, which can allow square brackets */
+library (liberty_define) {
+  delay_model : "table_lookup" ;
+  simulation : false ;
+  capacitive_load_unit (1,pF) ;
+  leakage_power_unit : "1pW" ;
+  current_unit : "1A" ;
+  pulling_resistance_unit : "1kohm" ;
+  time_unit : "1ns" ;
+  voltage_unit : "1v" ;
+  library_features : "report_delay_calculation" ;
+  input_threshold_pct_rise : 50 ;
+  input_threshold_pct_fall : 50 ;
+  output_threshold_pct_rise : 50 ;
+  output_threshold_pct_fall : 50 ;
+  slew_lower_threshold_pct_rise : 30 ;
+  slew_lower_threshold_pct_fall : 30 ;
+  slew_upper_threshold_pct_rise : 70 ;
+  slew_upper_threshold_pct_fall : 70 ;
+  slew_derate_from_library : 1.0 ;
+  nom_process : 1.0 ;
+  nom_temperature : 85.0 ;
+  nom_voltage : 0.75 ;
+  type (bus8) {
+    base_type : "array";
+    data_type : "bit";
+    bit_width : 8;
+    bit_from : 7;
+    bit_to : 0;
+  }
+  define (original_pin, pin, string) ;
+  cell (not_cell) {
+    bus (A) {
+      bus_type : "bus8" ;
+      direction : "input" ;
+    }
+    pin (Y) {
+      function : !A[0] ;
+      direction : "output" ;
+      original_pin : A[0] ;
+    }
+  }
+}

tests/liberty_verilog/busdef2.lib.v.ok

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+(* blackbox =  1  *)
+(* leakage_power_unit = "1pW" *)
+module not_cell(A, Y);
+  input [7:0] A;
+  wire [7:0] A;
+  output Y;
+  wire Y;
+endmodule

tests/liberty_verilog/run-test.sh

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+#!/usr/bin/env bash
+set -e
+
+for x in *.lib; do
+	echo "Testing on $x.."
+	echo "read_liberty -lib $x" > test.ys
+	echo "write_verilog -blackboxes $x.v.tmp" >> test.ys
+	../../yosys -ql ${x%.lib}.log -s test.ys
+	sed '1,2d' $x.v.tmp > $x.v
+	diff $x.v $x.v.ok
+done