Assume x values for missing signal data in FST

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>

tests/sim/assume_x_first_step.ys

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+read_verilog simple_assign.v
+sim -r simple_assign.vcd -scope simple_assign

tests/sim/simple_assign.v

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+module simple_assign (
+    input wire in,
+    output wire out
+);
+
+    assign out = in;
+
+endmodule

tests/sim/simple_assign.vcd

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+$version Yosys $end
+$scope module simple_assign $end
+$var wire 1 n2 in $end
+$var wire 1 n1 out $end
+$upscope $end
+$enddefinitions $end
+#0
+#5
+b1 n1
+b1 n2
+#10
+b0 n1
+b0 n2