Eddie Hung
15188033da
Add variable length support to xilinx_srl
2019-08-21 17:34:40 -07:00
Eddie Hung
edec73fec1
abc9 to perform new 'map_ffs' before 'map_luts'
2019-08-21 15:37:55 -07:00
Eddie Hung
5ce0c31d0e
Add init support
2019-08-21 13:05:10 -07:00
Eddie Hung
076af2e617
Missing newline
2019-08-20 20:37:52 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
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[WIP] synth xilinx renaming, as per #1184
2019-08-20 12:55:26 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
d9fe4cccbf
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Eddie Hung
1c57b1e7ea
Update abc_* attr in ecp5 and ice40
2019-08-16 15:56:57 -07:00
Eddie Hung
562c9e3624
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
2019-08-16 15:40:53 -07:00
Eddie Hung
41191f1ea4
Merge pull request #1250 from bwidawsk/master
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techlibs/intel: Clean up Makefile
2019-08-16 14:07:09 -07:00
Eddie Hung
8a2480526f
Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310f54bf1631f
2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
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Add a few comments to document $alu and $lcu
2019-08-10 09:46:46 +02:00
Eddie Hung
041defc5a6
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34
A bit more on where $lcu comes from
2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957
Add more comments
2019-08-09 09:48:17 -07:00
Eddie Hung
dae7c59358
Add a few comments to document $alu and $lcu
2019-08-08 10:05:28 -07:00
Eddie Hung
9776084eda
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
Eddie Hung
675c1d4218
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
2019-08-07 16:29:38 -07:00
Eddie Hung
cc331cf70d
Add test
2019-08-07 16:29:38 -07:00
Eddie Hung
ea8ac8fd74
Remove ice40_unlut
2019-08-07 16:29:38 -07:00
Eddie Hung
6b314c8371
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
2019-08-07 16:29:38 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
David Shah
5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
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ecp5: Make cells_sim.v consistent with nextpnr
2019-08-07 15:35:29 +01:00
David Shah
a36fd8582e
ecp5: Make cells_sim.v consistent with nextpnr
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-07 14:19:31 +01:00
Clifford Wolf
4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix
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anlogic : Fix alu mapping
2019-08-07 12:30:52 +02:00
Eddie Hung
e5be9ff871
Fix spacing
2019-08-06 16:47:55 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Ben Widawsky
7de098ad45
techlibs/intel: Clean up Makefile
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Use GNU make's foreach iterator and remove nonexistent files. Gmake is
already a requirement of the build system.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-08-05 11:22:11 -07:00
Miodrag Milanovic
837cb0a1b9
anlogic : Fix alu mapping
2019-08-03 14:47:33 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix
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Fix formatting for msys2 mingw build
2019-08-02 16:37:57 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Eddie Hung
66806085db
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
Clifford Wolf
eb663c7579
Merge branch 'ZirconiumX-synth_intel_m9k'
2019-07-25 17:23:48 +02:00
Clifford Wolf
5c933e5110
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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intel: Make -noiopads the default
2019-07-25 17:19:54 +02:00
Eddie Hung
5248a902ef
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 06:44:17 -07:00
David Shah
ab607e896e
xilinx: Fix missing cell name underscore in cells_map.v
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-25 08:19:07 +01:00
Dan Ravensloft
49528ed3bd
intel: Make -noiopads the default
2019-07-24 10:38:15 +01:00
Dan Ravensloft
67b4ce06e0
intel: Map M9K BRAM only on families that have it
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This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
2019-07-23 18:11:11 +01:00
David Shah
80884d6f7b
ice40: Fix test_dsp_model.sh
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:57 +01:00
David Shah
79f14c7514
ice40/cells_sim.v: Fix sign of J and K partial products
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-19 17:33:41 +01:00
