David Shah ab607e896e xilinx: Fix missing cell name underscore in cells_map.v ... Signed-off-by: David Shah <dave@ds0.me>		2019-07-25 08:19:07 +01:00
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achronix	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
anlogic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
common	Revert "Add "synth -keepdc" option"	2019-07-09 10:14:23 -07:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
ecp5	Error out if -abc9 and -retime specified	2019-07-10 12:47:48 -07:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	2019-02-26 09:40:46 -08:00
ice40	Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix	2019-07-16 08:52:14 -07:00
intel	synth_intel: Warn about untested Quartus backend	2019-07-07 19:26:31 +01:00
sf2	Add link to SF2 / igloo2 macro library guide	2019-03-07 09:08:26 -08:00
xilinx	xilinx: Fix missing cell name underscore in cells_map.v	2019-07-25 08:19:07 +01:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00