Eddie Hung 5248a902ef Merge pull request #1224 from YosysHQ/xilinx_fix_ff ... xilinx: Fix missing cell name underscore in cells_map.v		2019-07-25 06:44:17 -07:00
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achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
common	gen_lut to return correctly sized LUT mask	2019-07-16 12:45:29 -07:00
coolrunner2	Unify usage of noflatten among architectures	2019-01-04 11:37:25 +01:00
easic	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
ecp5	synth_ecp5: rename dram to lutram everywhere.	2019-07-16 20:45:12 +00:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	ice40: Fix test_dsp_model.sh	2019-07-19 17:33:57 +01:00
intel	Merge pull request #1208 from ZirconiumX/intel_cleanups	2019-07-18 19:04:28 +01:00
sf2	Add link to SF2 / igloo2 macro library guide	2019-03-07 09:08:26 -08:00
xilinx	xilinx: Fix missing cell name underscore in cells_map.v	2019-07-25 08:19:07 +01:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00