1954 commits

Author	SHA1	Message	Date
Akash Levy	c94eac14b9	Remove GHDL and add mixed SV-VHDL support	2024-10-20 23:29:33 -07:00
Akash Levy	e2659247fc	Verific UPF eval working	2024-10-17 04:40:38 -07:00
Akash Levy	cafd4cbbe8	Merge branch 'YosysHQ:main' into main	2024-10-15 06:43:06 -07:00
Emil J. Tywoniak	81bbde62ca	verilog_parser: silence yynerrs warning	2024-10-15 08:32:55 -04:00
Akash Levy	469f5a707a	Merge branch 'YosysHQ:main' into main	2024-10-14 11:21:54 -07:00
Emil J	caf56ca3e8	Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip ... Represent string constants as strings	2024-10-14 06:42:54 -07:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Miodrag Milanovic	8d2b63bb8a	Set VHDL assert condition initial state if fed by FF	2024-10-11 16:32:21 +02:00
Akash Levy	48cb802599	Undo bound removal	2024-10-10 13:34:18 -07:00
Akash Levy	fdc4c54c66	Merge branch 'YosysHQ:main' into main	2024-10-07 07:27:27 -10:00
Martin Povišer	0aab8b4158	Merge pull request #4605 from povik/liberty-unit-delay ... read_liberty: Optionally import unit delay arcs	2024-10-07 16:11:51 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 ... New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	7989d53c58	read_xaiger2: Add help	2024-10-07 14:19:49 +02:00
Martin Povišer	f44a418212	read_xaiger2: Add casts to silence warnings	2024-10-07 12:27:54 +02:00
Martin Povišer	8d12492610	read_xaiger2: Fix detecting the end of extensions	2024-10-07 12:03:48 +02:00
Martin Povišer	2b1b5652f1	Adjust read_xaiger2 prints	2024-10-07 12:03:48 +02:00
Akash Levy	f76cb43ac7	Add bundle support	2024-10-05 01:35:03 -10:00
Akash Levy	dd487ca8a1	Updating Yosys	2024-10-03 01:46:09 -07:00
Akash Levy	5038bfa2af	Fix minor whitespace thing	2024-10-03 00:29:16 -07:00
Akash Levy	ec296736f5	Simplify multiport	2024-10-02 22:19:09 -07:00
Akash Levy	400ae0bbab	Prune RAM dimensions	2024-10-02 03:44:57 -07:00
Akash Levy	8bf86e8d1f	Undo	2024-10-02 03:30:30 -07:00
Akash Levy	ff0fd570d8	Revert mem but fix Verific frontend to remove ugliness	2024-10-02 01:17:01 -07:00
Akash Levy	ee0b083a1e	Merge branch 'YosysHQ:main' into main	2024-09-30 02:43:09 -07:00
rherveille	ce7db661a8	Added cast to type support (#4284)	2024-09-29 17:03:01 -04:00
Akash Levy	0610d6ccc2	Smallfix to get GHDL working	2024-09-27 06:38:42 -07:00
Akash Levy	bb2cdd61fe	Fix GHDL and bump yosys-slang	2024-09-27 04:43:59 -07:00
Akash Levy	5a27db1463	Smallfix	2024-09-27 03:31:30 -07:00
Akash Levy	f6d577aed1	Fix GHDL support	2024-09-27 03:14:15 -07:00
Akash Levy	0fd6e29e8e	Fixups	2024-09-23 04:25:10 -07:00
Akash Levy	0b8d951493	Add synopsys VHDL libs by default in GHDL	2024-09-23 04:05:27 -07:00
Akash Levy	69bf7875dd	Small edits	2024-09-22 07:52:58 -07:00
Akash Levy	d655766c49	Smallfix	2024-09-22 06:57:28 -07:00
Akash Levy	89f9035a98	Fix VHDL checking	2024-09-22 06:45:47 -07:00
Akash Levy	7d5dac7255	More apt location for whereami	2024-09-22 06:02:20 -07:00
Akash Levy	f1ab51ce5b	Clean up and remove hdl_file_sort	2024-09-22 05:58:17 -07:00
Akash Levy	f0b1d2cac5	Small changes	2024-09-22 01:11:26 -07:00
Akash Levy	4cf9bb86ca	Smallfix	2024-09-19 01:04:29 -07:00
Akash Levy	7988a61f8c	Use enable debug and switch order of Verific opt passes	2024-09-19 00:48:31 -07:00
Akash Levy	2d139c8735	Smallfix to remove top/bottom-bound attributes	2024-09-18 14:46:13 -07:00
Martin Povišer	f168b2f4b1	read_xaiger2: Update box handling	2024-09-18 16:55:02 +02:00
Martin Povišer	1ab7f29933	Start read_xaiger2 -sc_mapping	2024-09-18 16:42:56 +02:00
Martin Povišer	4976abb867	read_liberty: Optionally import unit delay arcs	2024-09-18 16:17:03 +02:00
Akash Levy	44789c9f6c	Move ram opt around	2024-09-16 18:56:48 -07:00
Akash Levy	285c8a3f66	Merge branch 'YosysHQ:main' into main	2024-09-12 11:14:15 -07:00
N. Engelhardt	c8b42b7d48	Merge pull request #4538 from RCoeurjoly/verific_bounds	2024-09-12 13:04:04 +02:00
Akash Levy	985de62d3c	Merge branch 'YosysHQ:main' into main	2024-09-11 16:01:37 -07:00
Emil J. Tywoniak	1372c47036	internal_stats: astnode (sizeof)	2024-09-11 11:34:20 +02:00
Roland Coeurjoly	bdc43c6592	Add left and right bound properties to wire. Add test. Fix printing ... for signed attributes Co-authored-by: N. Engelhardt <nak@yosyshq.com> Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>	2024-09-10 12:52:42 +02:00
Akash Levy	ce95ec1f9e	Add VHDL support via GHDL call	2024-09-05 13:24:38 -07:00