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Add left and right bound properties to wire. Add test. Fix printing

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for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
This commit is contained in:
Roland Coeurjoly 2024-08-21 16:21:29 +02:00
parent 27c1432253
commit bdc43c6592
6 changed files with 40 additions and 3 deletions
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13
frontends/verific/verific.cc
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@ -450,6 +450,19 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
auto type_range = nl->GetTypeRange(obj->Name());
if (!type_range)
return;
if (type_range->IsTypeScalar()) {
const long long bottom_bound = type_range->GetScalarRangeLeftBound();
const long long top_bound = type_range->GetScalarRangeRightBound();
const unsigned bit_width = type_range->NumElements();
RTLIL::Const bottom_const(bottom_bound, bit_width);
RTLIL::Const top_const(top_bound, bit_width);
if (bottom_bound < 0 || top_bound < 0) {
bottom_const.flags |= RTLIL::CONST_FLAG_SIGNED;
top_const.flags |= RTLIL::CONST_FLAG_SIGNED;
}
attributes.emplace(ID(bottom_bound), bottom_const);
attributes.emplace(ID(top_bound), top_const);
}
if (!type_range->IsTypeEnum())
return;
#ifdef VERIFIC_VHDL_SUPPORT