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Move ram opt around

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This commit is contained in:
Akash Levy 2024-09-16 18:56:48 -07:00
parent 76b072151d
commit 44789c9f6c
2 changed files with 8 additions and 5 deletions
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11
frontends/verific/verific.cc
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@ -3000,6 +3000,11 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
log(" Removing buffers for %s.\n", it->first.c_str());
nl->RemoveBuffers();
log(" Merging RAM write ports for %s.\n", it->first.c_str());
nl->MergeRamWritePorts();
log(" Merging RAMs for %s.\n", it->first.c_str());
nl->MergeRams();
log(" Balancing timing for %s.\n", it->first.c_str());
unsigned result = nl->BalanceTiming(0);
log(" Balance timing result before: %d\n", result);
@ -3018,10 +3023,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
log(" Performing final resource merging for %s.\n", it->first.c_str());
nl->OptimizeSameInputSubstractorComparator();
log(" Merging RAM write ports for %s.\n", it->first.c_str());
nl->MergeRamWritePorts();
log(" Merging RAMs for %s.\n", it->first.c_str());
nl->MergeRams();
log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
nl->InferClockEnableMux();
}
if (nl_done.count(it->first) == 0) {

2
yosys-slang

@ -1 +1 @@
Subproject commit 871e35a0a0785515afb9c0ef13474ca3f3820099
Subproject commit cc730372e3ac6aac50b46b445317f7a0abb68e57