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verilog_parser: silence yynerrs warning
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@ -464,6 +464,7 @@ static const AstNode *addAsgnBinopStmt(dict<IdString, AstNode*> *attr, AstNode *
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%%
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input: {
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(void)frontend_verilog_yynerrs;
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ast_stack.clear();
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ast_stack.push_back(current_ast);
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} design {
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