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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-10-15 06:43:06 -07:00 committed by GitHub
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frontends/verilog/verilog_parser.y
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@ -464,6 +464,7 @@ static const AstNode *addAsgnBinopStmt(dict<IdString, AstNode*> *attr, AstNode *
%%
input: {
(void)frontend_verilog_yynerrs;
ast_stack.clear();
ast_stack.push_back(current_ast);
} design {