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Revert mem but fix Verific frontend to remove ugliness

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This commit is contained in:
Akash Levy 2024-10-02 01:17:01 -07:00
parent afe3b18a04
commit ff0fd570d8
2 changed files with 3 additions and 4 deletions
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2
frontends/verific/verific.cc
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@ -1649,7 +1649,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
cell->parameters[ID::ABITS] = 32;
cell->parameters[ID::WIDTH] = memory->width;
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
cell->parameters[ID::PRIORITY] = 0;
}
}
}

5
kernel/mem.cc
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@ -783,11 +783,10 @@ namespace {
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
if (!is_compat) {
// Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
for (int j = 0; j < n_wr_ports; j++)
if (wr_wide_continuation[j] != State::S1)
mwr.priority_mask.push_back(false);
// mwr.priority_mask.push_back(priority_mask[j] == State::S1);
mwr.priority_mask.push_back(priority_mask[j] == State::S1);
}
res.wr_ports.push_back(mwr);
}