3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-05 23:05:47 +00:00

Revert mem but fix Verific frontend to remove ugliness

This commit is contained in:
Akash Levy 2024-10-02 01:17:01 -07:00
parent afe3b18a04
commit ff0fd570d8
2 changed files with 3 additions and 4 deletions

View file

@ -1649,7 +1649,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
cell->parameters[ID::ABITS] = 32;
cell->parameters[ID::WIDTH] = memory->width;
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
cell->parameters[ID::PRIORITY] = 0;
}
}
}