Emil J. Tywoniak
49cd3887a7
const2ast: add diagnostics tests
2025-06-16 21:48:12 +02:00
Krystine Sherwin
fa68299b25
tests/verific: Add chformal tests
2025-06-14 11:06:38 +12:00
Krystine Sherwin
45131f4425
chformal: Add -assert2cover option
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Also add to chformal tests.
2025-06-14 10:54:23 +12:00
KrystalDelusion
82888580ac
Merge pull request #5152 from garytwong/unique-if
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verilog: implement SystemVerilog unique/unique0/priority if semantics.
2025-06-13 09:56:53 +12:00
Emil J
c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector
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splitnets: handle single-bit vectors consistently
2025-06-11 22:47:48 +02:00
George Rennie
7160c91800
tests: add test for #5164 opt_dff -sat UAF
2025-06-06 23:46:23 +01:00
Emil J. Tywoniak
239c265093
splitnets: handle single-bit vectors consistently
2025-06-05 10:58:06 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
George Rennie
ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
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read_verilog: fix -1 constant used to correct post increment/decrement
2025-06-04 14:22:32 +01:00
Emil J
c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs
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aiger: fix -map and -vmap
2025-06-02 15:07:19 +02:00
George Rennie
97f51bb4b7
tests: add tests for task/function argument input/output copying
2025-05-31 01:21:06 +01:00
KrystalDelusion
545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global
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SystemVerilog: Fix typedef struct in global space
2025-05-31 09:59:26 +12:00
George Rennie
3790be114f
tests: add tests for verilog pre/post increment/decrement in expressions
2025-05-30 14:38:25 +01:00
Gary Wong
7b09dc31af
tests: add cases covering full_case and parallel_case semantics
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This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.
(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
2025-05-29 20:45:57 -06:00
George Rennie
3ef4c91c31
Merge pull request #5148 from georgerennie/george/convertible_to_int_fix
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Fix convertible_to_int handling of 32 bit unsigned ints with MSB set.
2025-05-29 10:33:12 +01:00
KrystalDelusion
489a12d6c1
Merge pull request #5141 from garytwong/unique-if
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Accept (and ignore) SystemVerilog unique/priority if.
2025-05-27 09:45:50 +12:00
George Rennie
353fd0f7f4
tests: test opt_expr for 32 bit unsigned shifts
2025-05-26 15:28:44 +01:00
Krystine Sherwin
995a893afd
Tests: Add svtypes/typedef_struct_global.ys
2025-05-26 12:16:58 +12:00
Gary Wong
73e45d29d6
Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
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The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.
These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical. But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
2025-05-24 08:44:04 -06:00
Emil J
18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose
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libcache: add -quiet and -verbose
2025-05-24 00:05:46 +02:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Gary Wong
9770ece187
Accept (and ignore) SystemVerilog unique/priority if.
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Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.
This affects only the grammar accepted; the behaviour of conditionals
is not changed. (But accepting this syntax will provide scope for
possible optimisations as future work.)
Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
2025-05-22 19:28:28 -06:00
George Rennie
6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl
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opt_expr: fix shift optimization with overflowing shift amount
2025-05-22 15:16:19 +01:00
KrystalDelusion
4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst
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Update fstlib
2025-05-16 09:22:52 +12:00
KrystalDelusion
f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole
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cutpoint: Re-add whole module optimization
2025-05-16 09:22:28 +12:00
Emil J
3823157c25
Merge pull request #5080 from akashlevy/muldiv_c
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Add `muldiv_c` peepopt
2025-05-15 11:03:25 +02:00
Emil J. Tywoniak
e5171d6aa1
verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Krystine Sherwin
afd5bbc7fa
fstdata.cc: Fix last step
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Includes test file for sanity checking simulation steps.
2025-05-12 13:18:19 +12:00
Adrien Prost-Boucle
6bf7587338
URAM mapping : Add test for 2048 x 144b
2025-05-10 14:53:56 +02:00
Emil Jiří Tywoniak
cbf069849e
aiger: add regression test for sliced output segfault
2025-05-09 16:01:47 +02:00
Emil J. Tywoniak
9d2f9f7557
libcache: fix test
2025-05-09 12:40:38 +02:00
George Rennie
d59380b3a0
tests: more complete testing of shift edgecases
2025-05-08 11:09:01 +02:00
George Rennie
af933b4f38
tests: check shifts by amounts that overflow int
2025-05-07 15:12:33 +02:00
Krystine Sherwin
7c89355b70
cutpoint: Re-add whole module optimization
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Also add a test script for it.
2025-05-06 09:57:34 +12:00
Krystine Sherwin
7c2b00c448
tests: Add default param test file
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Just loads, fails ASAN without fix.
2025-05-05 10:18:52 +12:00
Akash Levy
4bd91fbb11
Add muldiv_c peepopt pass
2025-04-30 08:06:59 -07:00
KrystalDelusion
bfe05965f9
Merge pull request #5066 from YosysHQ/george/opt_expr_shr_sign
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opt_expr: fix sign extension for shifts
2025-04-29 09:29:10 +12:00
N. Engelhardt
84c49e1f33
Merge pull request #5041 from jix/declockgate-v2
2025-04-28 13:31:11 +00:00
George Rennie
70a44f035c
tests: test opt_expr constant shift edge cases
2025-04-26 12:40:04 +02:00
KrystalDelusion
6564810ae3
Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned
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ice40_dsp: fix const handling
2025-04-26 11:15:02 +12:00
Emil J. Tywoniak
9631f6ece5
liberty: fix tests
2025-04-23 20:20:43 +00:00
Mike Inouye
bf8aece4e4
Add test to verify that the liberty format is properly parsed.
2025-04-23 18:40:35 +00:00
Emil J
6a2f2f1818
Merge pull request #5031 from suisseWalter/fix_sequential_area
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stat: fix sequential area not being included in addition/multiplication
2025-04-21 11:02:40 +02:00
cwalter
41375a5f05
create testcase to check correct addition of areas.
2025-04-20 16:44:22 +02:00
clemens
01d80c7403
add testcase
2025-04-19 20:41:10 +02:00
Jannis Harder
31d6d0ac17
formalff: Fix -declockgate test and missing emit for memories
2025-04-18 18:57:59 +02:00
Jannis Harder
bd154a7188
formalff: Add -declockgate option
2025-04-18 17:44:34 +02:00
Jannis Harder
7f7ad87b7b
Merge pull request #5033 from jix/liberty-fixes
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liberty: More robust parsing
2025-04-17 09:24:42 +02:00
Emil J. Tywoniak
c555add231
liberty: Test non-ascii characters
2025-04-17 00:20:18 +02:00
