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tests: Add default param test file
Just loads, fails ASAN without fix.
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24
tests/verilog/param_default.ys
Normal file
24
tests/verilog/param_default.ys
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@ -0,0 +1,24 @@
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logger -expect-no-warnings
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read_verilog << EOF
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module bar (
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input portname
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);
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parameter paramname = 7;
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endmodule
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module empty (
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);
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bar #() barinstance ();
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endmodule
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module implicit (
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);
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bar #(.paramname()) barinstance (.portname());
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endmodule
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module explicit (
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input a
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);
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bar #(.paramname(3)) barinstance (.portname(a));
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endmodule
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EOF
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