Eddie Hung
5eda5fc7eb
Remove -icells
2019-08-20 12:41:11 -07:00
Eddie Hung
be9e4f1b67
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
...
Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
d9fe4cccbf
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
Eddie Hung
526e081342
Add arrival times for SRL outputs
2019-08-19 15:15:43 -07:00
Eddie Hung
b71212ddea
Add BRAM arrival times
2019-08-19 12:46:35 -07:00
Eddie Hung
2f86366087
Add reference to source of Tclktoq timing
2019-08-19 12:39:22 -07:00
Eddie Hung
d02ef8c73f
Add 'abc_arrival' attribute for flop outputs
2019-08-19 11:32:18 -07:00
Eddie Hung
f25837f8e8
Update box timings
2019-08-19 11:31:40 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
Miodrag Milanovic
4a32e29445
Merge remote-tracking branch 'upstream/master' into anlogic_fixes
2019-08-18 11:47:46 +02:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
1c57b1e7ea
Update abc_* attr in ecp5 and ice40
2019-08-16 15:56:57 -07:00
Eddie Hung
562c9e3624
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
2019-08-16 15:40:53 -07:00
Eddie Hung
41191f1ea4
Merge pull request #1250 from bwidawsk/master
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techlibs/intel: Clean up Makefile
2019-08-16 14:07:09 -07:00
Eddie Hung
261daffd9d
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-15 12:19:47 -07:00
Eddie Hung
e35dfc5ab5
Only swap ports if $mul and not $__mul
2019-08-13 16:52:15 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Eddie Hung
ed4b2834ef
Add assign PCOUT = P to DSP48E1
2019-08-13 12:19:26 -07:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Eddie Hung
2a1b98d478
Add DSP_A_MAXWIDTH_PARTIAL, refactor
2019-08-13 10:21:24 -07:00
David Shah
edff79a25a
xilinx: Rework labels for faster Verilator testing
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-13 10:29:42 +01:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
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A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
8a2480526f
Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310f54bf1631f
2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Miodrag Milanovic
5f561bdcb1
Proper arith for Anlogic and use standard pass
2019-08-12 20:21:36 +02:00
Miodrag Milanovic
2897fe4d09
Fix formating
2019-08-11 17:05:24 +02:00
Miodrag Milanovic
ead2b52b5a
one bit enable signal
2019-08-11 13:59:39 +02:00
Miodrag Milanovic
aa0c37722a
fix mixing signals on FF mapping
2019-08-11 11:40:15 +02:00
Miodrag Milanovic
853c755a0c
Replaced custom step with setundef
2019-08-11 11:01:46 +02:00
Miodrag Milanovic
e609537e38
Fixed data width
2019-08-11 10:46:48 +02:00
Miodrag Milanovic
8c8100e0df
Adding new pass to fix carry chain
2019-08-11 10:17:49 +02:00
Miodrag Milanovic
b3a91d6508
cleanup
2019-08-11 08:37:56 +02:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
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Add a few comments to document $alu and $lcu
2019-08-10 09:46:46 +02:00
Eddie Hung
6d254f2de8
Add wreduce to synth_ice40 -dsp as well
2019-08-09 17:05:56 -07:00
Eddie Hung
0b5b56c1ec
Pack partial-product adder DSP48E1 packing
2019-08-09 15:19:33 -07:00
Eddie Hung
041defc5a6
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34
A bit more on where $lcu comes from
2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957
Add more comments
2019-08-09 09:48:17 -07:00
Miodrag Milanovic
d51b135e33
Fix CO
2019-08-09 12:37:10 +02:00
Miodrag Milanovic
7a860c5623
Merge remote-tracking branch 'upstream/master' into efinix
2019-08-09 09:46:37 +02:00
