1736 commits

Author	SHA1	Message	Date
Eddie Hung	d223e11a72	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 22:28:35 -08:00
Eddie Hung	5cd3d3db0a	Remove redundant flatten	2019-11-22 22:28:10 -08:00
Eddie Hung	08f85e6438	Stray dump	2019-11-22 20:53:48 -08:00
Eddie Hung	2c5dfd802d	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 17:24:45 -08:00
Eddie Hung	4fdcf8f7d7	Add another test with constant driver	2019-11-22 17:23:34 -08:00
Eddie Hung	74ea438136	Add testcase for signal used as part input part output	2019-11-22 16:52:55 -08:00
Eddie Hung	0806b8e398	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	2019-11-22 16:50:56 -08:00
Eddie Hung	8779faf789	Cleanup spacing	2019-11-22 16:50:09 -08:00
Eddie Hung	2ef2e2c040	Add testcase	2019-11-22 16:48:11 -08:00
Eddie Hung	bd56161775	Merge branch 'eddie/clkpart' into xaig_dff	2019-11-22 15:38:48 -08:00
Eddie Hung	c761fa49b7	Missing endmodule	2019-11-22 12:37:57 -08:00
Clifford Wolf	72d2ef6fd0	Merge pull request #1511 from YosysHQ/dave/always ... sv: Error checking for always_comb, always_latch and always_ff	2019-11-22 15:32:29 +01:00
Marcin Kościelnicki	e110df9c48	gowin: Remove show command from tests.	2019-11-22 14:49:35 +01:00
Eddie Hung	6841e3b1c2	Another sloppy mistake!	2019-11-21 16:33:20 -08:00
Eddie Hung	fe36275234	Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff	2019-11-21 16:32:52 -08:00
Eddie Hung	39fdcb892b	async2sync -> clk2fflogic	2019-11-21 16:27:34 -08:00
Eddie Hung	5a30e3ac3b	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	2019-11-21 16:15:25 -08:00
Eddie Hung	911a152b39	Add test	2019-11-21 16:13:28 -08:00
David Shah	49b670ca38	sv: Add tests for SV always types ... Signed-off-by: David Shah <dave@ds0.me>	2019-11-21 21:06:28 +00:00
Eddie Hung	cd9e830b67	Add multi clock test	2019-11-20 13:28:55 -08:00
Eddie Hung	1cc106452f	Add a equiv test too	2019-11-19 17:05:14 -08:00
Eddie Hung	90c5ca330c	Add two tests	2019-11-19 16:57:58 -08:00
Clifford Wolf	7ea0a5937b	Merge pull request #1449 from pepijndevos/gowin ... Improvements for gowin support	2019-11-19 17:29:27 +01:00
Marcin Kościelnicki	15232a48af	Fix #1462, #1480.	2019-11-19 08:57:39 +01:00
Marcin Kościelnicki	38e72d6e13	Fix #1496.	2019-11-18 04:16:48 +01:00
Pepijn de Vos	32f0296df1	Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin	2019-11-16 12:43:17 +01:00
Pepijn de Vos	ab8c521030	fix fsm test with proper clock enable polarity	2019-11-11 17:51:26 +01:00
Miodrag Milanovic	3e0ffe05a7	Fixed tests	2019-11-11 15:41:33 +01:00
Pepijn de Vos	0e5dbc4abc	fix wide luts	2019-11-06 19:48:18 +01:00
Pepijn de Vos	df8390f5df	don't cound exact luts in big muxes; futile and fragile	2019-10-30 14:58:25 +01:00
Pepijn de Vos	903f997391	add tristate buffer and test	2019-10-28 15:18:01 +01:00
Pepijn de Vos	9517525224	do not use wide luts in testcase	2019-10-28 14:40:12 +01:00
Pepijn de Vos	8226f2db0b	ALU sim tweaks	2019-10-24 13:39:43 +02:00
Pepijn de Vos	83fbfe0964	Add some tests ... Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram	2019-10-21 16:25:15 +02:00
Miodrag Milanovic	190b40341a	fixed error	2019-10-18 13:15:36 +02:00
Miodrag Milanovic	9bd9db56c8	Unify verilog style	2019-10-18 12:50:24 +02:00
Miodrag Milanovic	12383f37b2	Common memory test now shared	2019-10-18 12:33:35 +02:00
Miodrag Milanovic	477702b8c9	Remove not needed tests	2019-10-18 12:20:35 +02:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00
Miodrag Milanovic	ab98f2dccf	fix yosys path	2019-10-18 11:18:53 +02:00
Miodrag Milanovic	56f9482675	Fix path to yosys	2019-10-18 11:12:03 +02:00
Miodrag Milanovic	c2ec7ca703	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00
Miodrag Milanovic	3c41599ee1	Add async2sync	2019-10-18 11:00:27 +02:00
Miodrag Milanović	b4d7650548	Merge branch 'master' into mmicko/efinix	2019-10-18 10:54:28 +02:00
Miodrag Milanović	66fca65b58	Merge branch 'master' into mmicko/anlogic	2019-10-18 10:53:56 +02:00
Miodrag Milanović	0b0b0cc0d9	Merge branch 'master' into eddie/pr1352	2019-10-18 10:52:50 +02:00
Miodrag Milanovic	b659082e4a	hierarchy - proc reorder	2019-10-18 09:13:06 +02:00
Miodrag Milanovic	46af9a0ff7	hierarchy - proc reorder	2019-10-18 09:06:43 +02:00
Miodrag Milanovic	0d60902fd9	hierarchy - proc reorder	2019-10-18 09:04:02 +02:00
Miodrag Milanovic	e6ad714d20	hierarchy - proc reorder	2019-10-18 08:06:57 +02:00