2474 commits

Author	SHA1	Message	Date
Eddie Hung	584c680691	Add abc_arrival to SRL*	2019-08-21 11:27:42 -07:00
Eddie Hung	076af2e617	Missing newline	2019-08-20 20:37:52 -07:00
Eddie Hung	b7a48e3e0f	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-20 20:18:17 -07:00
Eddie Hung	64d62710de	Oops	2019-08-20 20:07:38 -07:00
Eddie Hung	c26c556384	xilinx to use abc_map.v with -max_iter 1	2019-08-20 19:47:11 -07:00
Eddie Hung	6b1b03d9f7	ecp5: remove DPR16X4 from abc_unmap.v	2019-08-20 19:20:17 -07:00
Eddie Hung	d46dc9c5b4	ecp5 to use -max_iter 1	2019-08-20 19:18:36 -07:00
Eddie Hung	55acf3120f	ecp5 to use abc_map.v and _unmap.v	2019-08-20 18:59:03 -07:00
Eddie Hung	343039496b	Add reference to FD* timing	2019-08-20 18:22:58 -07:00
Eddie Hung	f1a206ba03	Revert "Remove sequential extension" ... This reverts commit 091bf4a18b.	2019-08-20 18:17:14 -07:00
Eddie Hung	091bf4a18b	Remove sequential extension	2019-08-20 18:16:37 -07:00
Eddie Hung	bbab608691	Remove SRL* delays from cells_sim.v	2019-08-20 18:14:40 -07:00
Eddie Hung	aa2d3af631	LUTMUX -> LUTMUX6	2019-08-20 18:08:07 -07:00
Eddie Hung	30a379b5b6	Cleanup techmap in map_luts	2019-08-20 17:59:31 -07:00
Eddie Hung	3b52d6e29c	Move techmap abc_map.v into map_luts	2019-08-20 17:55:12 -07:00
Eddie Hung	54284aaa98	Remove delays from abc_map.v	2019-08-20 17:52:27 -07:00
Eddie Hung	96f00e9147	Typo	2019-08-20 17:51:50 -07:00
Eddie Hung	8f666ebac1	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 17:36:14 -07:00
Eddie Hung	e273ed5275	Wrap SRL{16,32} too	2019-08-20 15:09:38 -07:00
Eddie Hung	808f07630f	Wrap LUTRAMs in order to capture comb/seq behaviour	2019-08-20 14:49:11 -07:00
Eddie Hung	0079e9b4a6	Add LUTRAM delays	2019-08-20 13:53:38 -07:00
Eddie Hung	8d0cffaf20	Remove mapping rules	2019-08-20 13:11:39 -07:00
Eddie Hung	33960dd3d8	Merge pull request #1209 from YosysHQ/eddie/synth_xilinx ... [WIP] synth xilinx renaming, as per #1184	2019-08-20 12:55:26 -07:00
Eddie Hung	5eda5fc7eb	Remove -icells	2019-08-20 12:41:11 -07:00
Eddie Hung	be9e4f1b67	Use abc_{map,unmap,model}.v	2019-08-20 12:39:11 -07:00
Eddie Hung	c4d4c6db3f	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-20 12:00:12 -07:00
Eddie Hung	14c03861b6	Merge pull request #1304 from YosysHQ/eddie/abc9_refactor ... Refactor abc9 to use port attributes, not module attributes	2019-08-20 11:59:31 -07:00
Eddie Hung	d9fe4cccbf	Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx	2019-08-20 11:57:52 -07:00
Eddie Hung	526e081342	Add arrival times for SRL outputs	2019-08-19 15:15:43 -07:00
Eddie Hung	b71212ddea	Add BRAM arrival times	2019-08-19 12:46:35 -07:00
Eddie Hung	2f86366087	Add reference to source of Tclktoq timing	2019-08-19 12:39:22 -07:00
Eddie Hung	d02ef8c73f	Add 'abc_arrival' attribute for flop outputs	2019-08-19 11:32:18 -07:00
Eddie Hung	f25837f8e8	Update box timings	2019-08-19 11:31:40 -07:00
Eddie Hung	ba2261e21a	Move from cell attr to module attr	2019-08-19 11:18:33 -07:00
Eddie Hung	2f4e0a5388	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-08-19 10:07:27 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
Eddie Hung	e301440a0b	Use attributes instead of params	2019-08-19 09:51:49 -07:00
Miodrag Milanovic	4a32e29445	Merge remote-tracking branch 'upstream/master' into anlogic_fixes	2019-08-18 11:47:46 +02:00
whitequark	101235400c	Merge branch 'master' into eddie/pr1266_again	2019-08-18 08:04:10 +00:00
Eddie Hung	24c934f1af	Merge branch 'eddie/abc9_refactor' into xaig_dff	2019-08-16 16:51:22 -07:00
Eddie Hung	1c57b1e7ea	Update abc_* attr in ecp5 and ice40	2019-08-16 15:56:57 -07:00
Eddie Hung	562c9e3624	Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules	2019-08-16 15:40:53 -07:00
Eddie Hung	41191f1ea4	Merge pull request #1250 from bwidawsk/master ... techlibs/intel: Clean up Makefile	2019-08-16 14:07:09 -07:00
Eddie Hung	261daffd9d	Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp	2019-08-15 12:19:47 -07:00
Eddie Hung	e35dfc5ab5	Only swap ports if $mul and not $__mul	2019-08-13 16:52:15 -07:00
Marcin Kościelnicki	3c75a72feb	move attributes to wires	2019-08-13 19:36:59 +00:00
Eddie Hung	ed4b2834ef	Add assign PCOUT = P to DSP48E1	2019-08-13 12:19:26 -07:00
Marcin Kościelnicki	49765ec19e	minor review fixes	2019-08-13 18:05:49 +00:00
Eddie Hung	2a1b98d478	Add DSP_A_MAXWIDTH_PARTIAL, refactor	2019-08-13 10:21:24 -07:00
David Shah	edff79a25a	xilinx: Rework labels for faster Verilator testing ... Signed-off-by: David Shah <dave@ds0.me>	2019-08-13 10:29:42 +01:00