mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-01 12:55:53 +00:00
Code Activity

Add reference to FD* timing

Browse source
This commit is contained in:
Eddie Hung 2019-08-20 18:22:58 -07:00
parent 091bf4a18b
commit 343039496b
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/cells_sim.v
View file

@ -211,6 +211,8 @@ endmodule
`endif
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
module FDRE ((* abc_arrival=303 *) output reg Q,
input C, CE, D, R);
parameter [0:0] INIT = 1'b0;