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Code Activity
yosys/techlibs
History
Eddie Hung c26c556384 xilinx to use abc_map.v with -max_iter 1
2019-08-20 19:47:11 -07:00
..
achronix
anlogic anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
common Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
coolrunner2 Fix spacing 2019-08-06 16:47:55 -07:00
easic
ecp5 ecp5: remove DPR16X4 from abc_unmap.v 2019-08-20 19:20:17 -07:00
gowin Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
greenpak4
ice40 Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 2019-08-20 11:59:31 -07:00
intel techlibs/intel: Clean up Makefile 2019-08-05 11:22:11 -07:00
sf2
xilinx xilinx to use abc_map.v with -max_iter 1 2019-08-20 19:47:11 -07:00
.gitignore