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Remove sequential extension

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This commit is contained in:
Eddie Hung 2019-08-20 18:16:37 -07:00
parent bbab608691
commit 091bf4a18b
9 changed files with 68 additions and 730 deletions
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97
techlibs/xilinx/abc_map.v
View file

@ -20,103 +20,6 @@
// ============================================================================
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
wire \$nextQ ;
\$__ABC_FDRE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_R_INVERTED(IS_R_INVERTED),
.CLK_POLARITY(!IS_C_INVERTED),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire \$nextQ ;
\$__ABC_FDRE_1 #(
.INIT(|0),
.CLK_POLARITY(1'b0),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_CLR_INVERTED(IS_CLR_INVERTED),
.CLK_POLARITY(!IS_C_INVERTED),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDCE_1 #(
.INIT(INIT),
.CLK_POLARITY(1'b0),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDPE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
.CLK_POLARITY(!IS_C_INVERTED),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDPE_1 #(
.INIT(INIT),
.CLK_POLARITY(1'b0),
.EN_POLARITY(1'b1)
) _TECHMAP_REPLACE_ (
.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
endmodule
module RAM32X1D (
output DPO, SPO,
input D,

89
techlibs/xilinx/abc_model.v
View file

@ -26,94 +26,6 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
: (S0 ? I1 : I0);
endmodule
module \$__ABC_FF_ (input C, D, output Q);
endmodule
(* abc_box_id = 1000 *)
module \$__ABC_ASYNC (input A, S, output Y);
endmodule
(* abc_box_id=1001, lib_whitebox, abc_flop *)
module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule
(* abc_box_id=1002, lib_whitebox, abc_flop *)
module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
endmodule
(* abc_box_id=1003, lib_whitebox, abc_flop *)
module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id=1004, lib_whitebox, abc_flop *)
module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !CLR) ? D : \$pastQ ;
endmodule
(* abc_box_id=1005, lib_whitebox, abc_flop *)
module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id=1006, lib_whitebox, abc_flop *)
module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = (CE && !PRE) ? D : \$pastQ ;
endmodule
(* abc_box_id=2000 *)
module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
endmodule
@ -121,7 +33,6 @@ endmodule
module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
endmodule
module \$__ABC_RAM32X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc_arrival=1153 *) output DPO, SPO,

119
techlibs/xilinx/abc_unmap.v
View file

@ -20,125 +20,6 @@
// ============================================================================
module \$__ABC_ASYNC (input A, S, output Y);
assign Y = A;
endmodule
module \$__ABC_FDRE (output Q,
input C,
input CE,
input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDRE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_R_INVERTED(IS_R_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
);
endmodule
module \$__ABC_FDRE_1 (output Q,
input C,
input CE,
input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
FDRE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
);
endmodule
module \$__ABC_FDCE (output Q,
input C,
input CE,
input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDCE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_CLR_INVERTED(IS_CLR_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
);
endmodule
module \$__ABC_FDCE_1 (output Q,
input C,
input CE,
input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
FDCE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
);
endmodule
module \$__ABC_FDPE (output Q,
input C,
input CE,
input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter CLK_POLARITY = !IS_C_INVERTED;
parameter EN_POLARITY = 1'b1;
FDPE #(
.INIT(INIT),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_D_INVERTED(IS_D_INVERTED),
.IS_PRE_INVERTED(IS_PRE_INVERTED),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_FDPE_1 (output Q,
input C,
input CE,
input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
parameter CLK_POLARITY = 1'b0;
parameter EN_POLARITY = 1'b1;
FDPE_1 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
);
endmodule
module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule

41
techlibs/xilinx/abc_xc7.box
View file

@ -38,47 +38,6 @@ CARRY4 4 1 10 8
592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114
# Box to emulate async behaviour of FD[CP]*
# Inputs: A S
# Outputs: Y
$__ABC_ASYNC 1000 0 2 1
0 764
# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
# reflect the -46ps Tsu
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
# Inputs: C CE D R \$pastQ
# Outputs: Q
FDRE 1001 1 5 1
0 151 0 446 0
# Inputs: C CE D R \$pastQ
# Outputs: Q
FDRE_1 1002 1 5 1
0 151 0 446 0
# Inputs: C CE CLR D \$pastQ
# Outputs: Q
FDCE 1003 1 5 1
0 151 806 0 0
# Inputs: C CE CLR D \$pastQ
# Outputs: Q
FDCE_1 1004 1 5 1
0 151 806 0 0
# Inputs: C CE D PRE \$pastQ
# Outputs: Q
FDPE 1005 1 5 1
0 151 0 806 0
# Inputs: C CE D PRE \$pastQ
# Outputs: Q
FDPE_1 1006 1 5 1
0 151 0 806 0
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
# Inputs: A S0 S1 S2 S3 S4 S5

24
techlibs/xilinx/cells_sim.v
View file

@ -211,7 +211,8 @@ endmodule
`endif
module FDRE (output reg Q, input C, CE, D, R);
module FDRE ((* abc_arrival=303 *) output reg Q,
input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -223,7 +224,8 @@ module FDRE (output reg Q, input C, CE, D, R);
endcase endgenerate
endmodule
module FDSE (output reg Q, input C, CE, D, S);
module FDSE ((* abc_arrival=303 *) output reg Q,
input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -235,7 +237,8 @@ module FDSE (output reg Q, input C, CE, D, S);
endcase endgenerate
endmodule
module FDCE (output reg Q, input C, CE, D, CLR);
module FDCE ((* abc_arrival=303 *) output reg Q,
input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -249,7 +252,8 @@ module FDCE (output reg Q, input C, CE, D, CLR);
endcase endgenerate
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
module FDPE ((* abc_arrival=303 *) output reg Q,
input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -263,25 +267,29 @@ module FDPE (output reg Q, input C, CE, D, PRE);
endcase endgenerate
endmodule
module FDRE_1 (output reg Q, input C, CE, D, R);
module FDRE_1 ((* abc_arrival=303 *) output reg Q,
input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
module FDSE_1 (output reg Q, input C, CE, D, S);
module FDSE_1 ((* abc_arrival=303 *) output reg Q,
input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR);
module FDCE_1 ((* abc_arrival=303 *) output reg Q,
input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
module FDPE_1 (output reg Q, input C, CE, D, PRE);
module FDPE_1 ((* abc_arrival=303 *) output reg Q,
input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;

6
techlibs/xilinx/synth_xilinx.cc
View file

@ -379,8 +379,6 @@ struct SynthXilinxPass : public ScriptPass
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
if (abc9)
techmap_args += " -map +/xilinx/ff_map.v";
run("techmap " + techmap_args);
run("clean");
}
@ -411,11 +409,9 @@ struct SynthXilinxPass : public ScriptPass
// has performed any necessary retiming
if (!nosrl || help_mode)
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
std::string techmap_args = "-map +/xilinx/lut_map.v";
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
if (abc9)
techmap_args += " -map +/xilinx/abc_unmap.v";
else
techmap_args += " -map +/xilinx/ff_map.v";
run("techmap " + techmap_args);
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");