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Merge remote-tracking branch 'origin/master' into xc7dsp

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This commit is contained in:
Eddie Hung 2019-08-20 20:18:17 -07:00
commit b7a48e3e0f
133 changed files with 4172 additions and 2286 deletions
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22
techlibs/ecp5/cells_sim.v
View file

@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
endmodule
// ---------------------------------------
(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1, COUT);
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
(* abc_carry *) input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry *) output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES";
@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
input WRE, WCK,
input [3:0] RAD,
(* abc_scc_break *) input [3:0] DI,
(* abc_scc_break *) input [3:0] WAD,
(* abc_scc_break *) input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";

1
techlibs/ice40/Makefile.inc
View file

@ -4,7 +4,6 @@ OBJS += techlibs/ice40/ice40_braminit.o
OBJS += techlibs/ice40/ice40_ffssr.o
OBJS += techlibs/ice40/ice40_ffinit.o
OBJS += techlibs/ice40/ice40_opt.o
OBJS += techlibs/ice40/ice40_unlut.o
GENFILES += techlibs/ice40/brams_init1.vh
GENFILES += techlibs/ice40/brams_init2.vh

32
techlibs/ice40/arith_map.v
View file

@ -44,35 +44,21 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
`ifdef _ABC
\$__ICE40_FULL_ADDER carry (
\$__ICE40_CARRY_WRAPPER #(
// A[0]: 1010 1010 1010 1010
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
.LUT(16'b 0110_1001_1001_0110)
) fadd (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.I0(1'b0),
.I3(C[i]),
.CO(CO[i]),
.O(Y[i])
);
`else
SB_CARRY carry (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.CO(CO[i])
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(AA[i]),
.I2(BB[i]),
.I3(C[i]),
.O(Y[i])
);
`endif
end endgenerate
assign X = AA ^ BB;

23
techlibs/ice40/cells_map.v
View file

@ -62,26 +62,21 @@ module \$lut (A, Y);
endmodule
`endif
`ifdef _ABC
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
`ifndef NO_ADDER
module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(A),
.I2(B),
.I3(CI),
.O(O)
\$lut #(
.WIDTH(4),
.LUT(LUT)
) lut (
.A({I0,A,B,I3}),
.Y(O)
);
endmodule
`endif

10
techlibs/ice40/cells_sim.v
View file

@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry *) output CO,
output O,
input A,
input B,
(* abc_carry *) input CI
);
SB_CARRY carry (
.I0(A),
.I1(B),

106
techlibs/ice40/ice40_unlut.cc
View file

@ -1,106 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static SigBit get_bit_or_zero(const SigSpec &sig)
{
if (GetSize(sig) == 0)
return State::S0;
return sig[0];
}
static void run_ice40_unlut(Module *module)
{
SigMap sigmap(module);
for (auto cell : module->selected_cells())
{
if (cell->type == "\\SB_LUT4")
{
SigSpec inbits;
inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
sigmap.apply(inbits);
log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
cell->type ="$lut";
cell->setParam("\\WIDTH", 4);
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({
get_bit_or_zero(cell->getPort("\\I0")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I3"))
}));
cell->setPort("\\Y", cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");
cell->unsetPort("\\I3");
cell->unsetPort("\\O");
cell->check();
}
}
}
struct Ice40UnlutPass : public Pass {
Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" ice40_unlut [options] [selection]\n");
log("\n");
log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
// if (args[argidx] == "-???") {
// continue;
// }
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
run_ice40_unlut(module);
}
} Ice40UnlutPass;
PRIVATE_NAMESPACE_END

13
techlibs/ice40/synth_ice40.cc
View file

@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
run("read_verilog -icells -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -298,8 +298,10 @@ struct SynthIce40Pass : public ScriptPass
{
if (nocarry)
run("techmap");
else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
else {
run("ice40_wrapcarry");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
if (retime || help_mode)
run(abc + " -dff", "(only if -retime)");
run("ice40_opt");
@ -314,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
run("opt_merge");
run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
}
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("ice40_ffinit");
@ -343,13 +345,12 @@ struct SynthIce40Pass : public ScriptPass
else
wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
}
else
run(abc + " -dress -lut 4", "(skip if -noabc)");
}
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("clean");
run("ice40_unlut");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
}

9
techlibs/ice40/tests/test_arith.ys
View file

@ -1,6 +1,5 @@
read_verilog test_arith.v
synth_ice40
techmap -map ../cells_sim.v
rename test gate
read_verilog test_arith.v
@ -8,3 +7,11 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
synth_ice40 -top gate
read_verilog test_arith.v
rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter

20
techlibs/intel/Makefile.inc
View file

@ -5,20 +5,10 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v))
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v))
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))
#$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/arith_map.v))
#$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/arith_map.v))
# Add the cell models and mappings for the VQM backend
families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))

4
techlibs/xilinx/Makefile.inc
View file

@ -32,8 +32,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))

28
techlibs/xilinx/cells_sim.v
View file

@ -181,8 +181,14 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry *) output [3:0] CO,
output [3:0] O,
(* abc_carry *) input CI,
input CYINIT,
input [3:0] DI, S
);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
@ -289,10 +295,12 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc_box_id = 5, abc_scc_break="D,WE" *)
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -307,10 +315,12 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 6, abc_scc_break="D,WE" *)
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -325,10 +335,12 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 7, abc_scc_break="D,WE" *)
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;

0
techlibs/xilinx/drams.txt → techlibs/xilinx/lutrams.txt
View file

0
techlibs/xilinx/drams_map.v → techlibs/xilinx/lutrams_map.v
View file

31
techlibs/xilinx/synth_xilinx.cc
View file

@ -64,13 +64,13 @@ struct SynthXilinxPass : public ScriptPass
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -nobram\n");
log(" disable inference of block rams\n");
log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -nodram\n");
log(" disable inference of distributed rams\n");
log(" -nolutram\n");
log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -nosrl\n");
log(" disable inference of shift registers\n");
log(" do not use distributed SRL cells in output netlist\n");
log("\n");
log(" -nocarry\n");
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
@ -107,7 +107,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, nodsp, abc9;
bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@ -121,7 +121,7 @@ struct SynthXilinxPass : public ScriptPass
vpr = false;
nocarry = false;
nobram = false;
nodram = false;
nolutram = false;
nosrl = false;
nocarry = false;
nowidelut = false;
@ -190,8 +190,8 @@ struct SynthXilinxPass : public ScriptPass
nobram = true;
continue;
}
if (args[argidx] == "-nodram") {
nodram = true;
if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
nolutram = true;
continue;
}
if (args[argidx] == "-nosrl") {
@ -306,7 +306,7 @@ struct SynthXilinxPass : public ScriptPass
run("opt_clean");
}
if (check_label("bram", "(skip if '-nobram')")) {
if (check_label("map_bram", "(skip if '-nobram')")) {
if (help_mode) {
run("memory_bram -rules +/xilinx/{family}_brams.txt");
run("techmap -map +/xilinx/{family}_brams_map.v");
@ -323,20 +323,23 @@ struct SynthXilinxPass : public ScriptPass
}
}
if (check_label("dram", "(skip if '-nodram')")) {
if (!nodram || help_mode) {
run("memory_bram -rules +/xilinx/drams.txt");
run("techmap -map +/xilinx/drams_map.v");
if (check_label("map_lutram", "(skip if '-nolutram')")) {
if (!nolutram || help_mode) {
run("memory_bram -rules +/xilinx/lutrams.txt");
run("techmap -map +/xilinx/lutrams_map.v");
}
}
if (check_label("fine")) {
if (check_label("map_ffram")) {
if (widemux > 0)
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently
else
run("opt -fast -full");
run("memory_map");
}
if (check_label("fine")) {
run("dffsr2dff");
run("dff2dffe");
if (help_mode) {