Eddie Hung
a4f641f230
Do not overwrite LUT param
2019-08-28 18:46:53 -07:00
Eddie Hung
d46d38e4d5
Trailing comma
2019-08-28 17:25:54 -07:00
Eddie Hung
f5b4bc847c
Adapt to $__ICE40_CARRY_WRAPPER
2019-08-28 17:25:05 -07:00
Eddie Hung
e569f13870
Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"
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This reverts commit 2aedee1f0e
2019-08-28 17:22:44 -07:00
Eddie Hung
2aedee1f0e
Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with
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CARRY_WRAPPER in the same way since I0 and I3 could be used
2019-08-28 17:07:36 -07:00
Eddie Hung
077e9d4ada
Update box size and timings
2019-08-28 17:07:24 -07:00
Eddie Hung
129df7184a
Update to new $__ICE40_CARRY_WRAPPER
2019-08-28 17:07:07 -07:00
Eddie Hung
9314a0a42e
Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
2019-08-28 10:51:39 -07:00
David Shah
13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr
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ecp5: Add GSR and SGSR support
2019-08-28 12:44:02 +01:00
Marcin Kościelnicki
d361f5ab79
xilinx: Add SRLC16E primitive.
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Fixes #1331 .
2019-08-27 20:27:12 +02:00
David Shah
fc001b4731
ecp5: Add GSR support
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-27 13:07:06 +01:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
d7051b90de
Add undocumented feature
2019-08-23 16:41:32 -07:00
Eddie Hung
20f4d191b5
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:24:19 -07:00
Eddie Hung
509c353fe9
Forgot one
2019-08-23 11:23:50 -07:00
Eddie Hung
0d0ad15898
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-23 11:23:31 -07:00
Eddie Hung
a270af00cc
Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Clifford Wolf
151db528e4
Fix missing newline at end of file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:09:37 +02:00
Clifford Wolf
2c8c8b3c74
Merge pull request #1289 from mmicko/anlogic_fixes
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Anlogic fixes and optimization
2019-08-22 18:09:10 +02:00
Clifford Wolf
4c449caf9b
Fix missing newline at end of file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:06:36 +02:00
Clifford Wolf
4d37710e82
Merge pull request #1281 from mmicko/efinix
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Initial support for Efinix Trion series FPGAs
2019-08-22 18:06:02 +02:00
Eddie Hung
076af2e617
Missing newline
2019-08-20 20:37:52 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
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[WIP] synth xilinx renaming, as per #1184
2019-08-20 12:55:26 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
d9fe4cccbf
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Miodrag Milanovic
4a32e29445
Merge remote-tracking branch 'upstream/master' into anlogic_fixes
2019-08-18 11:47:46 +02:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Eddie Hung
1c57b1e7ea
Update abc_* attr in ecp5 and ice40
2019-08-16 15:56:57 -07:00
Eddie Hung
562c9e3624
Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
2019-08-16 15:40:53 -07:00
Eddie Hung
41191f1ea4
Merge pull request #1250 from bwidawsk/master
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techlibs/intel: Clean up Makefile
2019-08-16 14:07:09 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Marcin Kościelnicki
49765ec19e
minor review fixes
2019-08-13 18:05:49 +00:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
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A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
8a2480526f
Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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This reverts commit c851dc1310f54bf1631f
2019-08-12 12:06:45 -07:00
Miodrag Milanovic
5f561bdcb1
Proper arith for Anlogic and use standard pass
2019-08-12 20:21:36 +02:00
Miodrag Milanovic
2897fe4d09
Fix formating
2019-08-11 17:05:24 +02:00
Miodrag Milanovic
ead2b52b5a
one bit enable signal
2019-08-11 13:59:39 +02:00
Miodrag Milanovic
aa0c37722a
fix mixing signals on FF mapping
2019-08-11 11:40:15 +02:00
Miodrag Milanovic
853c755a0c
Replaced custom step with setundef
2019-08-11 11:01:46 +02:00
Miodrag Milanovic
e609537e38
Fixed data width
2019-08-11 10:46:48 +02:00
Miodrag Milanovic
8c8100e0df
Adding new pass to fix carry chain
2019-08-11 10:17:49 +02:00
Miodrag Milanovic
b3a91d6508
cleanup
2019-08-11 08:37:56 +02:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
a469d1a64a
Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc
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Add a few comments to document $alu and $lcu
2019-08-10 09:46:46 +02:00
Eddie Hung
041defc5a6
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
