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Merge branch 'master' into mwk/xilinx_bufgmap

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Eddie Hung 2019-08-23 11:24:19 -07:00
commit 20f4d191b5
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techlibs/xilinx/cells_sim.v
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@ -343,7 +343,7 @@ module RAM64X1D (
(* clkbuf_sink *)
input WCLK,
(* abc_scc_break *)
input WE,
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);