2043 commits

Author	SHA1	Message	Date
Akash Levy	fa97c4830e	Generalize muxadd to muxorder	2025-03-06 16:57:47 -08:00
Akash Levy	881080a827	Merge upstream	2025-03-05 07:54:26 -08:00
Akash Levy	9d3b7f7474	Merge branch 'YosysHQ:main' into main	2025-02-26 09:51:44 -08:00
Emil J	b4a169527d	Merge pull request #4894 from YosysHQ/emil/abstract ... Add `abstract` pass for formal verification	2025-02-25 11:16:37 +01:00
Emil J. Tywoniak	3f60a2cc67	abstract: test -slice from:to for -init	2025-02-25 00:22:14 +01:00
Emil J. Tywoniak	3cb7054e53	abstract: test -slice for all modes, -rtlilslice for -init	2025-02-25 00:18:16 +01:00
Emil J. Tywoniak	5bd18613bb	abstract: test -init	2025-02-19 23:03:43 +01:00
Alain Dargelas	929c817384	splitnets new options	2025-02-19 09:43:53 -08:00
Emil J. Tywoniak	34e3fcbb31	abstract: test -value	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	d3a90021ad	abstract: test -state	2025-02-18 17:08:45 +01:00
Jannis Harder	7cd822b7f5	rtlil: Add {from,to}_hdl_index methods to Wire ... In the past we had the occasional bug due to some place not handling all 4 combinations of upto/downto and zero/nonzero start_offset correctly.	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	387d0de383	abstract: -state allow partial abstraction, don't use buffer-normalized mode	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	6027030215	abstract: -value MVP, use buffer-normalized mode	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	4637fa74e3	abstract: -init MVP	2025-02-18 17:08:45 +01:00
Emil J. Tywoniak	e4ca7b8846	abstract: -state MVP	2025-02-18 17:08:45 +01:00
Akash Levy	33c72b0f25	Merge branch 'YosysHQ:main' into main	2025-02-15 15:54:28 -08:00
Akash Levy	c4254a9a95	Final cleanup	2025-02-14 10:18:13 -08:00
Akash Levy	1b13b5d6ea	Move segv and reenable loops.v test	2025-02-14 10:02:30 -08:00
Akash Levy	fd811ddaee	Cleanup	2025-02-14 08:48:27 -08:00
Akash Levy	9cc82c7044	Revert clocking.ys	2025-02-13 20:32:17 -08:00
Akash Levy	c8c97ea00b	Revert back to using Verific naming	2025-02-13 19:40:33 -08:00
Krystine Sherwin	db5b76edc1	Add test for shifting by INT_MAX ... Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.	2025-02-14 14:01:27 +13:00
Akash Levy	4e45a86e12	Merge branch 'YosysHQ:main' into main	2025-02-06 12:29:43 -08:00
Jannis Harder	40c690b030	extract_fa: Add test case	2025-01-30 18:45:06 +01:00
Akash Levy	2ae7490adf	Disable Verific blackbox checks (different from our preferred approach)	2025-01-21 05:46:40 -08:00
Akash Levy	bca65ceff7	opt_clean was removing the unused bits annotation	2025-01-16 19:48:31 -08:00
Akash Levy	ab338b33cb	Use equiv_opt -nocells to ensure everything is ok since dffs retain their name	2025-01-16 19:40:18 -08:00
Akash Levy	67a93dc76d	scopeinfo inverted	2025-01-16 19:36:42 -08:00
Akash Levy	90f980eb66	Changed boolopt naming	2025-01-16 19:36:27 -08:00
Akash Levy	53ed83fcac	Rename verific to import in tests and update README explanation	2025-01-16 19:34:02 -08:00
Alain Dargelas	84c6be1edd	Add splitfanout tests	2025-01-16 12:04:53 -08:00
Alain Dargelas	31a5197a1c	muxadd and muldiv_c peepopt	2025-01-15 16:57:19 -08:00
Akash Levy	5c514e00a4	Sync with upstream	2025-01-13 17:20:59 -08:00
N. Engelhardt	7e3990b681	Merge pull request #4837 from YosysHQ/json_scopinfo_opt ... write_json: add option to include $scopeinfo cells	2025-01-10 09:57:22 +00:00
N. Engelhardt	77b28442a5	emit $scopeinfo cells by default	2025-01-08 14:47:46 +01:00
Martin Povišer	ca0ace66bc	Merge pull request #4817 from povik/macc_v2-1 ... macc: Stop using the B port	2025-01-08 14:42:51 +01:00
N. Engelhardt	dab7905cbe	write_json: add option to include $scopeinfo cells	2025-01-08 13:33:56 +01:00
Martin Povišer	652a1b9806	macc: Stop using the B port ... The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`	2025-01-08 13:03:35 +01:00
Akash Levy	443613da69	Merge branch 'YosysHQ:main' into main	2025-01-07 00:56:19 -05:00
Martin Povišer	41e4aa8f0a	Merge pull request #4819 from povik/wreduce-resign ... wreduce: Optimize signedness when possible	2025-01-06 15:27:55 +01:00
Akash Levy	1dcf75d175	Sync	2024-12-19 21:40:30 -08:00
Emil J	6ab5be4a0e	Merge pull request #4814 from YosysHQ/emil/make-test-fasterer ... test: every test everywhere all at once	2024-12-18 19:02:39 +01:00
Martin Povišer	08778917db	wreduce: Optimize signedness when possible	2024-12-16 12:57:08 +01:00
Emil J. Tywoniak	6240aec433	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
Akash Levy	1242db626f	Merge remote-tracking branch 'upstream/main'	2024-12-12 22:49:19 -08:00
N. Engelhardt	378864d33b	bound attributes: handle vhdl null ranges	2024-12-12 11:42:39 +01:00
Emil J. Tywoniak	603e5eb30a	test: every test everywhere all at once	2024-12-12 01:28:36 +01:00
Akash Levy	caaef5ac14	Merge branch 'YosysHQ:main' into main	2024-12-11 12:00:34 -08:00
N. Engelhardt	03033ab6d4	add more tests for bounds attributes, fix attributes appearing in verilog	2024-12-11 16:11:02 +01:00
Martin Povišer	4bd6061709	Merge pull request #4799 from povik/wrapcell-unused ... wrapcell: Optionally track unused outputs	2024-12-10 21:16:28 +01:00