Merge pull request #4817 from povik/macc_v2-1

macc: Stop using the B port

tests/alumacc/macc_b_port_compat.ys

@@ -0,0 +1,50 @@
+# We don't set the B port on $macc cells anymore,
+# test compatibility with older RTLIL files which can
+# have the B port populated
+
+read_verilog <<EOF
+module gold(input signed [2:0] a1, input signed [2:0] b1,
+			input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
+  wire signed [3:0] ab1;
+  assign ab1 = a1 * b1;
+  assign y = ab1 + a2*b2 + c + d + 1;
+endmodule
+EOF
+prep
+
+# test the model for $macc including the retired B parameter
+# matches the gold module
+read_rtlil <<EOF
+attribute \src "<<EOF:1.1-4.10"
+module \gate
+  wire width 3 input 1 signed \a1
+  wire width 2 input 3 \a2
+  wire width 3 input 2 signed \b1
+  wire width 4 input 4 \b2
+  wire input 5 \c
+  wire input 6 \d
+  wire width 4 output 7 signed \y
+
+  cell $macc $1
+    parameter \A_WIDTH 12
+    parameter \B_WIDTH 3
+    parameter \CONFIG 20'01010000011011010011
+    parameter \CONFIG_WIDTH 20
+    parameter \Y_WIDTH 4
+    connect \A { \a2 \b2 \b1 \a1 }
+    connect \B { \d \c 1'1 }
+    connect \Y \y
+  end
+end
+EOF
+
+design -save gold_gate
+equiv_make gold gate equiv
+equiv_induct equiv
+equiv_status -assert equiv
+
+design -load gold_gate
+maccmap gate
+equiv_make gold gate equiv
+equiv_induct equiv
+equiv_status -assert equiv

tests/alumacc/run-test.sh

@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done