Disable Verific blackbox checks (different from our preferred approach)

2025-04-20 23:56:38 +00:00 · 2025-01-21 05:46:40 -08:00 · 2025-01-21 05:46:40 -08:00 · 2ae7490adf
parent e73d51dbf0
commit 2ae7490adf
4 changed files with 1 additions and 0 deletions
--- a/tests/verific/README.md
+++ b/tests/verific/README.md
@ -5,3 +5,4 @@
 - `bounds`: relies on using Verific's VHDL frontend
 - `memory_semantics`: relies on initial values being retained, which we do not want
 - `rom_case`: relies on using Verific's VHDL frontend
+- `blackbox*`: we need different behavior for parametrized blackboxes
--- a/tests/verific/blackbox.ys.DISABLED
+++ b/tests/verific/blackbox.ys.DISABLED
--- a/tests/verific/blackbox_empty.ys.DISABLED
+++ b/tests/verific/blackbox_empty.ys.DISABLED
--- a/tests/verific/blackbox_ql.ys.DISABLED
+++ b/tests/verific/blackbox_ql.ys.DISABLED