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Merge branch 'YosysHQ:main' into main

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Akash Levy 2024-12-11 12:00:34 -08:00 • committed by GitHub
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21 changed files with 432 additions and 137 deletions
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9
tests/techmap/dfflibmap-sim.v
View file

@ -20,3 +20,12 @@ always @(posedge CLK, posedge CLEAR, posedge PRESET)
assign QN = ~Q;
endmodule
module dffe(input CLK, EN, D, output reg Q, output QN);
always @(negedge CLK)
if (EN) Q <= D;
assign QN = ~Q;
endmodule

32
tests/techmap/dfflibmap.lib
View file

@ -5,7 +5,7 @@ library(test) {
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "!CLK";
}
}
pin(D) {
direction : input;
}
@ -19,7 +19,7 @@ library(test) {
pin(QN) {
direction: output;
function : "IQN";
}
}
}
cell (dffsr) {
area : 6;
@ -30,7 +30,7 @@ library(test) {
preset : "PRESET";
clear_preset_var1 : L;
clear_preset_var2 : L;
}
}
pin(D) {
direction : input;
}
@ -50,6 +50,30 @@ library(test) {
pin(QN) {
direction: output;
function : "IQN";
}
}
}
cell (dffe) {
area : 6;
ff("IQ", "IQN") {
next_state : "(D&EN) | (IQ&!EN)";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(EN) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

32
tests/techmap/dfflibmap.ys
View file

@ -1,14 +1,15 @@
read_verilog -icells <<EOT
module top(input C, D, S, R, output [9:0] Q);
module top(input C, D, E, S, R, output [11:0] Q);
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
assign Q[9:5] = ~Q[4:0];
assign Q[11:6] = ~Q[5:0];
endmodule
@ -29,23 +30,25 @@ design -load orig
dfflibmap -liberty dfflibmap.lib
clean
select -assert-count 4 t:$_NOT_
select -assert-count 5 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
select -assert-count 1 t:dffe
select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -prepare -liberty dfflibmap.lib
select -assert-count 9 t:$_NOT_
select -assert-count 11 t:$_NOT_
select -assert-count 1 t:$_DFF_N_
select -assert-count 4 t:$_DFFSR_PPP_
select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
select -assert-count 1 t:$_DFFE_NP_
select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_DFFE_NP_ t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -map-only -liberty dfflibmap.lib
select -assert-count 5 t:$_NOT_
select -assert-count 6 t:$_NOT_
select -assert-count 0 t:dffn
select -assert-count 1 t:dffsr
@ -54,20 +57,22 @@ dfflibmap -prepare -liberty dfflibmap.lib
dfflibmap -map-only -liberty dfflibmap.lib
clean
select -assert-count 4 t:$_NOT_
select -assert-count 5 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
select -assert-count 1 t:dffe
select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -prepare -liberty dfflibmap_dffn.lib -liberty dfflibmap_dffsr.lib
dfflibmap -map-only -liberty dfflibmap_dffn.lib -liberty dfflibmap_dffsr.lib
dfflibmap -prepare -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr.lib
dfflibmap -map-only -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr.lib
clean
select -assert-count 4 t:$_NOT_
select -assert-count 5 t:$_NOT_
select -assert-count 1 t:dffn
select -assert-count 1 t:dffe
select -assert-count 4 t:dffsr
select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i
select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i
design -load orig
dfflibmap -liberty dfflibmap.lib -dont_use *ffn
@ -75,3 +80,4 @@ clean
select -assert-count 0 t:dffn
select -assert-count 5 t:dffsr
select -assert-count 1 t:dffe

23
tests/techmap/dfflibmap_dffn.lib
View file

@ -1,23 +0,0 @@
library(test) {
cell (dffn) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

47
tests/techmap/dfflibmap_dffn_dffe.lib Normal file
View file

@ -0,0 +1,47 @@
library(test) {
cell (dffn) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
cell (dffe) {
area : 6;
ff("IQ", "IQN") {
next_state : "(D&EN) | (IQ&!EN)";
clocked_on : "!CLK";
}
pin(D) {
direction : input;
}
pin(EN) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
}
pin(QN) {
direction: output;
function : "IQN";
}
}
}

32
tests/various/wrapcell.ys
View file

@ -18,8 +18,40 @@ EOF
wreduce
wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}
check -assert
select -assert-count 2 top/t:OR_2_3_3
select -assert-count 1 top/t:OR_3_4_4
select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 %% top/t:* %D
select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
select -assert-mod-count 2 A:bar=w3 A:bar=w4
design -reset
read_verilog <<EOF
module top(
input [1:0] a,
input [2:0] b,
output [2:0] y,
input [2:0] a2,
input [3:0] b2,
output [3:0] y2,
input [1:0] a3,
input [2:0] b3,
output [2:0] y3
);
assign y = a | (*keep*) b;
assign y2 = a2 | (*keep*) b2;
wire [2:0] y3_ = a3 | (*keep*) b3;
assign y3 = {y3_[2], y3_[0]};
endmodule
EOF
opt_clean
wreduce
wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}{%unused}
check -assert
select -assert-count 1 top/t:OR_2_3_3
select -assert-count 1 top/t:OR_2_3_3_unused_Y[1]
select -assert-count 1 top/t:OR_3_4_4
select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 top/t:OR_2_3_3_unused_Y[1] %% top/t:* %D
select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
select -assert-mod-count 3 A:bar=w3 A:bar=w4