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13896 commits 93 branches 53 tags 45 MiB
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1818 commits

Author SHA1 Message Date
Miodrag Milanović
598d010349
Merge pull request #4504 from YosysHQ/nanoxplore 
NanoXplore synthesis
 2024-09-03 10:19:44 +02:00
George Rennie
8206951f77 proc_dff: add tests 2024-08-28 16:24:47 +01:00
Roland Coeurjoly
91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Emil J
e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix 
peepopt: avoid shift-amount underflow
 2024-08-19 15:45:46 +02:00
Miodrag Milanovic
54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
3848563600 Update tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
34f08bc639 Enable nanoxplore tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
65d2ebac9d fix test 2024-08-15 17:50:36 +02:00
Lofty
b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Lofty
b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty
b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
b4a17cccc3 add few more tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
93543bd874 add lut tests 2024-08-15 17:50:36 +02:00
Martin Povišer
c35f5e379c Extend liberty tests 2024-08-13 18:47:36 +02:00
N. Engelhardt
9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J. Tywoniak
01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
chunlin min
3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
Tony Min
d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
Tony Min
6fe0e00050
Add missing u sram init (#3) 
add missing INIT for uSRAM
 2024-07-04 16:39:10 -04:00
chunlin min
8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min
e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
phsauter
34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Marian Buschsieweke
7f89a45ad7 cxxxrtl: fix use of format specifiers in test 
This fix a few instances of incorrect (and non-portable) use of format
specifiers.
 2024-06-11 07:22:39 +01:00
Asherah Connor
dc69365258 cxxrtl: failing test: unconnected blackbox outputs don't compile. 2024-06-07 14:24:27 +03:00
Martin Povišer
4b67f3757f
Merge pull request #4404 from YosysHQ/povik/bbox_derive 
box_derive: New command to derive modules for boxes
 2024-05-31 19:09:18 +02:00
Martin Povišer
97fedff383 box_derive: Tune the test 2024-05-29 20:42:11 +02:00
Martin Povišer
bff2443af8 box_derive: Finish the test 2024-05-21 16:34:49 +02:00
Martin Povišer
c0a196173a Rename bbox_derive to box_derive 2024-05-21 16:18:03 +02:00
N. Engelhardt
24f9329c67
Merge pull request #4367 from YosysHQ/lofty/intel_alm-drop-quartus 
intel_alm: drop quartus support
 2024-05-21 16:01:23 +02:00
Martin Povišer
557db4ea46 bbox_drive: Add an incomplete test 2024-05-21 14:57:49 +02:00
Martin Povišer
b143e5678f cellmatch: Rename the special design to $cellmatch 2024-05-03 16:42:41 +02:00
Martin Povišer
913bc87c44 cellmatch: Add test 2024-05-03 16:42:41 +02:00
Emil J. Tywoniak
a833f05036 techmap: add dynamic cell type test 2024-05-03 13:53:49 +02:00
Lofty
8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
George Rennie
4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
N. Engelhardt
e8ec19c273 add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality) 2024-04-12 13:51:06 +02:00
N. Engelhardt
b87327d1b9 fix hierarchy -generate mode handling of cells 2024-04-12 13:38:33 +02:00
Miodrag Milanovic
0c7ac36dcf Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
Martin Povišer
dc746080f5
Merge pull request #4298 from povik/kogge-stone 
techmap: Add a Kogge-Stone option for `$lcu` mapping
 2024-04-08 16:46:06 +02:00
N. Engelhardt
8e8885e1cc
Merge pull request #4323 from YosysHQ/tests_update 
Tests update for latest more strict iverilog
 2024-04-08 15:10:59 +02:00
Miodrag Milanovic
4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Miodrag Milanovic
91e41d8c80 Move parameters to module declaration 2024-04-08 12:44:37 +02:00
Catherine
d9a4a42389 write_verilog: don't assign to a reg. 
Fixes #2035.
 2024-04-03 13:06:45 +02:00