mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
Merge pull request #4452 from phsauter/shiftadd-underflow-fix
peepopt: avoid shift-amount underflow
This commit is contained in:
commit
e0d3bbf3c3
2 changed files with 21 additions and 2 deletions
15
tests/opt/bug4413.ys
Normal file
15
tests/opt/bug4413.ys
Normal file
|
@ -0,0 +1,15 @@
|
|||
read_verilog <<EOT
|
||||
module top(
|
||||
input wire shift,
|
||||
input wire [4:0] data,
|
||||
output wire out
|
||||
);
|
||||
|
||||
wire [1:0] shift2 = shift - 1'b1;
|
||||
|
||||
assign out = data >> shift2;
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
equiv_opt -assert peepopt
|
Loading…
Add table
Add a link
Reference in a new issue