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Code Activity
11486 commits 121 branches 59 tags 72 MiB
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175 commits

Author SHA1 Message Date
Zachary Snow
bf15dbd0f7 sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
Miodrag Milanovic
957fdb328a Next dev cycle 2022-04-05 11:50:49 +02:00
Miodrag Milanovic
b63e0a0cae Release version 0.16 2022-04-05 11:49:37 +02:00
Miodrag Milanovic
0d3bf9e725 Update CHANGELOG and manual 2022-04-04 16:53:47 +02:00
Miodrag Milanovic
7be7f5e02e Next dev cycle 2022-03-04 11:37:18 +01:00
Miodrag Milanovic
07a43689d8 Release version 0.15 2022-03-04 11:36:03 +01:00
Miodrag Milanovic
3818e1160d Update CHANGELOG 2022-03-02 14:26:15 +01:00
Zachary Snow
15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Kamil Rakoczy
68c67c40ec
Fix access to whole sub-structs (#3086) 
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-02-14 14:34:20 +01:00
Zachary Snow
15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow
90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Miodrag Milanovic
818060880d Next dev cycle 2022-02-07 17:10:50 +01:00
Miodrag Milanovic
a4522d6282 Release version 0.14 2022-02-07 17:08:39 +01:00
Miodrag Milanovic
9647f6326f Update CHANGELOG and manual 2022-02-07 17:07:48 +01:00
Miodrag Milanovic
c428a894c0 Next dev cycle 2022-01-11 08:39:34 +01:00
Miodrag Milanovic
8b1eafc3ad Release version 0.13 2022-01-11 08:35:50 +01:00
Miodrag Milanovic
64972360a8 Update CHANGELOG 2022-01-11 08:21:12 +01:00
Zachary Snow
aa35f24290 sv: auto add nosync to certain always_comb local vars 
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
 2022-01-07 22:53:22 -07:00
Zachary Snow
828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
Zachary Snow
8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Zachary Snow
7608985d2c fix width detection of array querying function in case and case item expressions 
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
 2021-12-17 21:22:08 -07:00
Miodrag Milanovic
c23cd00f30 Next dev cycle 2021-12-03 12:51:34 +01:00
Miodrag Milanovic
2156e20db5 Release version 0.12 2021-12-03 12:48:49 +01:00
Miodrag Milanovic
4792d925fc Update CHANGELOG and CODEOWNERS 2021-12-01 08:42:37 +01:00
Miodrag Milanovic
a28ee81be0 Next dev cycle 2021-11-05 12:52:24 +01:00
Miodrag Milanovic
360fed8e4d Release version 0.11 2021-11-05 12:47:38 +01:00
Miodrag Milanovic
051b234df6 Add missing changelog item 2021-11-05 10:08:50 +01:00
Miodrag Milanovic
c0edfa8788 Add missing items in CHANGELOG 2021-10-29 13:31:41 +02:00
Zachary Snow
e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Marcelina Kościelnicka
ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Miodrag Milanovic
070cad5f4b Prepare for next release cycle 2021-09-27 16:24:43 +02:00
Zachary Snow
d6fe6d4fb6 sv: support wand and wor of data types 
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
 2021-09-21 14:52:28 -04:00
Miodrag Milanović
1d52c07e9b
Updates for CHANGELOG (#2997) 
Added missing changes from git log and  group items
 2021-09-13 16:25:42 +02:00
Marcelina Kościelnicka
fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka
19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Marcelina Kościelnicka
9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka
dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
 2020-07-21 15:00:54 +02:00
Marcelina Kościelnicka
e3564b4502 Add dfflegalize pass. 2020-07-01 01:57:15 +02:00
Xiretza
c34cb90a20
Update CHANGELOG 2020-05-28 22:59:04 +02:00
Eddie Hung
c34d57de2e Update CHANGELOG and manual for departure from upstream 2020-04-27 12:08:45 -07:00
Eddie Hung
254d38ca67 select: add select -unset option 2020-04-16 10:51:58 -07:00
Eddie Hung
a9ec0defb9 kernel: add design -delete option 2020-04-16 08:05:18 -07:00
Marcelina Kościelnicka
38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Miodrag Milanovic
d8735b2913 Add to changelog 2020-02-17 15:08:35 +01:00
Rodrigo A. Melo
665a967d87
Merge branch 'master' into master 2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo
313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
David Shah
0488492ad2 Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:13:13 +00:00
Rodrigo Alejandro Melo
2774aae0f2 Removed a line jump into the CHANGELOG 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:56:01 -03:00
Rodrigo Alejandro Melo
7b3fe404ab $readmem[hb] file inclusion is now relative to the Verilog file 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 18:20:22 -03:00