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verilog: fix const func eval with upto variables

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Zachary Snow 2022-01-11 23:51:08 -07:00 • committed by Zachary Snow
parent ca876e7c12
commit 90bb47d181
5 changed files with 99 additions and 3 deletions
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@ -5,6 +5,10 @@ List of major changes and improvements between releases
Yosys 0.14 .. Yosys 0.14-dev
--------------------------
* Verilog
- Fixed evaluation of constant functions with variables or arguments with
reversed dimensions
Yosys 0.13 .. Yosys 0.14
--------------------------