mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-30 17:27:16 +00:00
Code Activity

techmap: Add _TECHMAP_CELLNAME_ special parameter.

Browse source 
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
This commit is contained in:
Marcelina Kościelnicka 2020-07-21 15:00:54 +02:00
parent 57af8499df
commit dc07ae9677
4 changed files with 50 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
CHANGELOG
View file

@ -39,7 +39,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Improvements in pmgen: slices, choices, define, generate
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
- Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "-match-init" option to "dff2dffs" pass
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
@ -69,6 +69,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added $divfloor and $modfloor cells
- Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
- Added "dfflegalize" pass
- Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
Yosys 0.8 .. Yosys 0.9
----------------------