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Fix access to whole sub-structs (#3086)

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* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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Kamil Rakoczy 2022-02-14 14:34:20 +01:00 • committed by GitHub
parent 59738c09be
commit 68c67c40ec
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7 changed files with 72 additions and 11 deletions
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@ -11,6 +11,9 @@ Yosys 0.14 .. Yosys 0.14-dev
- Fixed elaboration of dynamic range assignments where the vector is
reversed or is not zero-indexed
* SystemVerilog
- Added support for accessing whole sub-structures in expressions
Yosys 0.13 .. Yosys 0.14
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