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verilog: fix dynamic dynamic range asgn elab

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Zachary Snow 2022-01-17 23:18:12 -07:00 • committed by Zachary Snow
parent 90bb47d181
commit 15eb66b99d
4 changed files with 144 additions and 17 deletions
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@ -8,6 +8,8 @@ Yosys 0.14 .. Yosys 0.14-dev
* Verilog
- Fixed evaluation of constant functions with variables or arguments with
reversed dimensions
- Fixed elaboration of dynamic range assignments where the vector is
reversed or is not zero-indexed
Yosys 0.13 .. Yosys 0.14
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