mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-14 08:26:41 +00:00
Code Activity

Merge branch 'master' of https://github.com/YosysHQ/yosys

Browse source 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
This commit is contained in:
Rodrigo Alejandro Melo 2020-02-03 10:56:11 -03:00
commit 313a425bd5
12 changed files with 369 additions and 112 deletions
Download patch file Download diff file Expand all files Collapse all files

4
CHANGELOG
View file

@ -53,7 +53,9 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added support for flip-flops with synchronous reset to synth_xilinx
- Added support for flip-flops with reset and enable to synth_xilinx
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff)
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
- Added support for SystemVerilog wildcard port connections (.*)
- Added "xilinx_dffopt" pass
- Added "scratchpad" pass
- Added "abc9 -dff"