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verilog: support for time scale delay values

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Zachary Snow 2022-02-11 22:57:31 +01:00 • committed by Zachary Snow
parent 68c67c40ec
commit 15a4e900b2
4 changed files with 42 additions and 4 deletions
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@ -10,6 +10,7 @@ Yosys 0.14 .. Yosys 0.14-dev
reversed dimensions
- Fixed elaboration of dynamic range assignments where the vector is
reversed or is not zero-indexed
- Added frontend support for time scale delay values (e.g., `#1ns`)
* SystemVerilog
- Added support for accessing whole sub-structures in expressions