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Update CHANGELOG and manual for departure from upstream

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This commit is contained in:
Eddie Hung 2020-04-27 12:08:45 -07:00
parent a3fa9fd6e9
commit c34d57de2e
2 changed files with 5 additions and 4 deletions
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4
CHANGELOG
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@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev
* Various
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
@ -58,7 +58,6 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added support for SystemVerilog wildcard port connections (.*)
- Added "xilinx_dffopt" pass
- Added "scratchpad" pass
- Added "abc9 -dff"
- Added "synth_xilinx -dff"
- Improved support of $readmem[hb] Memory Content File inclusion
- Added "opt_lut_ins" pass
@ -66,6 +65,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Removed "dffsr2dff" (use opt_rmdff instead)
- Added "design -delete"
- Added "select -unset"
- Use YosysHQ/abc instead of upstream berkeley-abc/abc
Yosys 0.8 .. Yosys 0.9
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