2041 commits

Author	SHA1	Message	Date
Miodrag Milanović	29e8812bab	Merge pull request #4724 from YosysHQ/micko/blackbox_verific ... verific: fix blackbox regression and add test case	2024-11-25 15:06:54 +01:00
Akash Levy	c3d6821f7d	Removing compiler warnings and errors	2024-11-22 20:04:39 -08:00
George Rennie	4a057b3c44	read_rtlil: warn on assigns after switches in case rules	2024-11-21 22:41:13 +01:00
Alain Dargelas	97f5ef2056	indent	2024-11-21 11:31:36 -08:00
Alain Dargelas	dc9d61ed61	Loop info	2024-11-21 11:24:00 -08:00
Alain Dargelas	179bd25235	Loop info	2024-11-21 11:23:13 -08:00
Alain Dargelas	dde6a8d8f1	Loop info	2024-11-21 11:20:40 -08:00
Miodrag Milanovic	d6bd521487	verific : VHDL assert DFF initial value set on Verific library patch side	2024-11-21 13:43:26 +01:00
Akash Levy	bbbc292209	Smallfixes	2024-11-20 21:10:58 -08:00
Akash Levy	6a7e2d2572	Beginnings of UPF support	2024-11-20 20:36:29 -08:00
Akash Levy	2b39770f57	Update flags to be better	2024-11-20 20:36:12 -08:00
Akash Levy	06c87f6a2d	Smallfix	2024-11-19 17:42:36 -08:00
Akash Levy	5eaf627645	Undo Liberty stuff	2024-11-18 17:10:25 -08:00
Akash Levy	1a69c51c88	Merge branch 'YosysHQ:main' into main	2024-11-18 16:10:30 -08:00
Martin Povišer	1cb5fd08b7	Merge pull request #4682 from povik/read_liberty-extensions ... read_liberty extensions	2024-11-18 14:42:18 +01:00
Akash Levy	df0ce40841	blif fixes	2024-11-16 21:53:06 -08:00
Akash Levy	6be73e5c2e	Updates	2024-11-15 19:02:06 -08:00
Mike Inouye	06e3ac4415	Fix bug when setting Verific runtime string flags. ... Signed-off-by: Mike Inouye <mikeinouye@google.com>	2024-11-12 18:46:26 +00:00
Martin Povišer	0d5c412807	read_liberty: s/busses/buses/	2024-11-12 13:33:41 +01:00
Martin Povišer	28aa7b00ee	read_liberty: Start an -ignore_busses option	2024-11-12 13:26:38 +01:00
Martin Povišer	0e96e477a2	read_liberty: Defer handling of re-definitions ... Postpone handling re-definitions to after we have established the cell is not supposed to be ignored on the grounds of one of the user-provided flags.	2024-11-12 13:26:38 +01:00
Martin Povišer	c7e8d41600	read_liberty: Set area capacitance attributes	2024-11-12 13:26:38 +01:00
Akash Levy	a3b4789934	Smallfixes	2024-11-12 02:32:03 -08:00
Akash Levy	86d321a306	Undo blif frontend stuff	2024-11-12 01:30:06 -08:00
Akash Levy	83234d24f7	Switch from Synopsys register naming to preserve	2024-11-11 17:06:56 -08:00
Akash Levy	894c9816d3	Improve naming: big fix	2024-11-11 17:06:11 -08:00
Akash Levy	fa50434708	Merge branch 'YosysHQ:main' into main	2024-11-08 14:10:24 -08:00
Miodrag Milanovic	df391f5816	verific: fix blackbox regression and add test case	2024-11-08 14:57:04 +01:00
Akash Levy	1cba744712	Update	2024-11-04 17:01:41 -08:00
Krystine Sherwin	ee73a91f44	Remove references to ilang	2024-11-05 12:36:31 +13:00
George Rennie	dbfca1bdff	frontends/ast.cc: special-case zero width strings as "\0" ... * Fixes #4696	2024-11-01 17:19:28 +01:00
Alain Dargelas	615f523ef4	pass no_split_complex_ports to hierarchy command	2024-10-29 13:37:03 -07:00
Akash Levy	5e606722e3	Get autoidx reset working	2024-10-28 16:30:47 -07:00
Akash Levy	038c562493	VHDL support fix	2024-10-25 11:32:52 -07:00
Akash Levy	8e667e2e9f	Add documentation for VHDL library directory	2024-10-23 23:53:21 -07:00
Akash Levy	17c8567b02	Really tiny fixes	2024-10-23 22:03:00 -07:00
Akash Levy	3d127dff4a	Add set VHDL default library path	2024-10-21 01:22:56 -07:00
Akash Levy	c94eac14b9	Remove GHDL and add mixed SV-VHDL support	2024-10-20 23:29:33 -07:00
Akash Levy	e2659247fc	Verific UPF eval working	2024-10-17 04:40:38 -07:00
Akash Levy	cafd4cbbe8	Merge branch 'YosysHQ:main' into main	2024-10-15 06:43:06 -07:00
Emil J. Tywoniak	81bbde62ca	verilog_parser: silence yynerrs warning	2024-10-15 08:32:55 -04:00
Akash Levy	469f5a707a	Merge branch 'YosysHQ:main' into main	2024-10-14 11:21:54 -07:00
Emil J	caf56ca3e8	Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip ... Represent string constants as strings	2024-10-14 06:42:54 -07:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Miodrag Milanovic	8d2b63bb8a	Set VHDL assert condition initial state if fed by FF	2024-10-11 16:32:21 +02:00
Akash Levy	48cb802599	Undo bound removal	2024-10-10 13:34:18 -07:00
Akash Levy	fdc4c54c66	Merge branch 'YosysHQ:main' into main	2024-10-07 07:27:27 -10:00
Martin Povišer	0aab8b4158	Merge pull request #4605 from povik/liberty-unit-delay ... read_liberty: Optionally import unit delay arcs	2024-10-07 16:11:51 +02:00
Martin Povišer	74e92d10e8	Merge pull request #4593 from povik/aiger2 ... New aiger backend	2024-10-07 16:11:25 +02:00
Martin Povišer	7989d53c58	read_xaiger2: Add help	2024-10-07 14:19:49 +02:00