mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 08:35:32 +00:00
Code Activity

Smallfixes

Browse source
This commit is contained in:
Akash Levy 2024-11-20 21:10:58 -08:00
parent 08ff023510
commit bbbc292209
2 changed files with 5 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

7
frontends/verific/verific.cc
View file

@ -3010,7 +3010,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
}
#ifdef VERIFIC_UPF_SUPPORT
upf_file::Elaborate(top.c_str());
if (upf_file::GetActiveScope())
upf_file::Elaborate(top.c_str());
#endif
if (!verific_error_msg.empty())
@ -3535,9 +3536,9 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
// RuntimeFlags::SetVar("veri_preserve_assignments", 1); // SILIMATE: disable to improve optimization
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
// RuntimeFlags::SetVar("veri_preserve_drivers", 1); // SILIMATE: disable to improve optimization
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

2
kernel/ff.cc
View file

@ -263,7 +263,7 @@ FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initva
}
FfData FfData::slice(const std::vector<int> &bits) {
FfData res(module, initvals, NEW_ID2_SUFFIX("slice")); // SILIMATE: Improve the naming
FfData res(module, initvals, NEW_ID2); // SILIMATE: Improve the naming
res.sig_clk = sig_clk;
res.sig_ce = sig_ce;
res.sig_aload = sig_aload;