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Undo Liberty stuff

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This commit is contained in:
Akash Levy 2024-11-18 17:10:25 -08:00
parent e4095bf257
commit 5eaf627645
19 changed files with 0 additions and 571 deletions
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59
frontends/liberty/liberty.cc
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@ -545,12 +545,8 @@ struct LibertyFrontend : public Frontend {
std::map<std::string, std::tuple<int, int, bool>> global_type_map;
parse_type_map(global_type_map, parser.ast);
string leakage_power_unit = "";
for (auto cell : parser.ast->children)
{
if (cell->id == "leakage_power_unit")
leakage_power_unit = cell->value;
if (cell->id != "cell" || cell->args.size() != 1)
continue;
@ -562,8 +558,6 @@ struct LibertyFrontend : public Frontend {
RTLIL::Module *module = new RTLIL::Module;
std::string cell_name = RTLIL::escape_id(cell->args.at(0));
module->name = cell_name;
if (leakage_power_unit != "")
module->attributes["\\leakage_power_unit"] = leakage_power_unit;
if (flag_lib)
module->set_bool_attribute(ID::blackbox);
@ -580,12 +574,6 @@ struct LibertyFrontend : public Frontend {
for (auto node : cell->children)
{
if (node->id == "area")
module->attributes["\\area"] = node->value;
if (node->id == "cell_leakage_power")
module->attributes["\\LeakagePower"] = node->value;
if (node->id == "pin" && node->args.size() == 1) {
const LibertyAst *dir = node->find("direction");
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
@ -648,52 +636,6 @@ struct LibertyFrontend : public Frontend {
if (dir->value == "output" || dir->value == "inout")
wire->port_output = true;
}
if (node->id == "bundle" && node->args.size() == 1)
{
if (!flag_lib)
log_error("Error in cell %s: bundle interfaces are only supported in -lib mode.\n", log_id(cell_name));
const LibertyAst *dir = node->find("direction");
if (dir == nullptr) {
const LibertyAst *pin = node->find("pin");
if (pin != nullptr)
dir = pin->find("direction");
}
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
log_error("Missing or invalid direction for bundle %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
if (dir->value == "internal")
continue;
const LibertyAst *members = node->find("members");
if (!members)
log_error("Missing members for bundle %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
for (auto member : members->args)
{
Wire *wire = module->addWire(RTLIL::escape_id(member));
if (dir && dir->value == "inout") {
wire->port_input = true;
wire->port_output = true;
}
if (dir && dir->value == "input") {
wire->port_input = true;
continue;
}
if (dir && dir->value == "output")
wire->port_output = true;
if (flag_lib)
continue;
}
}
}
if (!flag_lib)
@ -830,4 +772,3 @@ skip_cell:;
} LibertyFrontend;
YOSYS_NAMESPACE_END