mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-04 14:25:47 +00:00
Code Activity

Add documentation for VHDL library directory

Browse source
This commit is contained in:
Akash Levy 2024-10-23 23:53:21 -07:00
parent 1953a42f0d
commit 8e667e2e9f
1 changed files with 5 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
frontends/verific/verific.cc
View file

@ -3168,6 +3168,11 @@ struct VerificPass : public Pass {
log("Add module to list of modules to ignore during parsing.\n");
log("\n");
log("\n");
log(" import -set_vhdl_default_library_path <path>\n");
log("\n");
log("VHDL default library path.\n");
log("\n");
log("\n");
#endif
log(" import -set-error <msg_id>..\n");
log(" import -set-warning <msg_id>..\n");