mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 00:26:40 +00:00
Code Activity

Removing compiler warnings and errors

Browse source
This commit is contained in:
Akash Levy 2024-11-22 20:04:39 -08:00
parent 70f7778560
commit c3d6821f7d
3 changed files with 9 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
frontends/verific/decorate_loops.h
View file

@ -17,6 +17,8 @@
*
*/
#ifdef VERIFIC_LINEFILE_INCLUDES_LOOPS
#include <stack>
/*
This Visitor decorates the AST with a loop ID attribute for all outer for loops.
All AST nodes contained within the subtree of an outer for-loop

6
frontends/verific/verific.cc
View file

@ -2881,6 +2881,8 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
}
continue;
}
#else
(void) top; // silience warnings
#endif
log_error("Can't find module/unit '%s'.\n", name);
}
@ -3794,7 +3796,9 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F" || args[argidx] == "-FF"))
{
unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
bool is_formal = false;
#endif
const char* filename = nullptr;
#ifndef SILIMATE_VERIFIC_EXTENSIONS
@ -3817,7 +3821,9 @@ struct VerificPass : public Pass {
continue;
} else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") {
verilog_mode = veri_file::SYSTEM_VERILOG;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (args[argidx] == "-formal") is_formal = true;
#endif
continue;
} else if (args[argidx].compare(0, 1, "-") == 0) {
cmd_error(args, argidx, "unknown option");

2
verific

@ -1 +1 @@
Subproject commit 182a3069817595bc743a969d97824abe9cf67de6
Subproject commit 419f9ac5219be9df31e9250090ce31fa69c00e43